Mixed Verilog and VHDL Designs
==============================

V-System/Plus allows you to simulate designs that are written
in VHDL and/or Verilog. VHDL source code is compiled by VCOM
and the resulting compiled design units (entities, architectures,
configurations, and packages) are stored in a library. Likewise,
Verilog source code is compiled by VLOG and the resulting design
units (modules and UDPs) are stored in a library.

Libraries can store any combination of VHDL and Verilog design
units, provided the design unit names do not overlap. Use VLIB
to create a new library. For example,

    vlib work

This creates a library named work. By default, both VCOM and VLOG
compile into the work library.

The boundaries between VHDL and Verilog are enforced at the level
of a design unit. This means that although a design unit must be
either all VHDL or all Verilog, it may instantiate design units
from either language. Any instance in the design hierarchy may be
a design unit from either HDL without restriction. This means
that the top-level design unit may be either VHDL or Verilog
and as you traverse the design hierarchy, instantiations may freely
switch back and forth between VHDL and Verilog.

Cross-HDL instantiation does not require any extra effort on the
user's part. As VSIM loads a design it detects cross-HDL
instantiations - made possible because a design unit's HDL
type can be determined as it is loaded from a library - and the
necessary adaptions and data type conversions are performed
automatically.

A VHDL instantiation of Verilog may associate VHDL signals and
values with Verilog ports and parameters. Likewise, a Verilog
instantiation of VHDL may associate Verilog nets and values with
VHDL ports and generics. VSIM automatically maps between the
HDL data types as follows:

VHDL generics:

    VHDL type     Verilog type
	-----------   ---------------
    integer       integer or real
    real          integer or real
    time          integer or real
    physical      integer or real
    enumeration   integer or real
    string        string literal

    When a scalar type receives a real value, the real is converted
    to an integer by truncating the decimal portion.

    Type time is treated specially: the Verilog number is converted
    to a time value according to the `timescale directive of the
    module.

    Physical and enumeration types receive a value that corresponds
    to the position number indicated by the Verilog number. In
    VHDL this is equivalent T'VAL(P), where T is the type, VAL is
    the predefined function attribute that returns a value given a
    position number, and P is the position number.

Verilog parameters:

    Verilog type    VHDL type 
    ------------    ---------
    integer         integer
    real            real
    string          string

    The type of a Verilog parameter is determined by its initial
    value.

VHDL and Verilog ports:

    The allowed VHDL types for ports connected to Verilog nets
    and for signals connected to Verilog ports are: bit, bit_vector,
    std_ulogic, std_ulogic_vector, vl_ulogic, vl_ulogic_vector,
    and their subtypes.

    The vl_logic type is an enumeration that defines the full state
    set for Verilog nets, including ambiguous strengths. The bit and
    std_logic types are convenient for most applications, but the
    vl_logic type is provided in case you need access to the full
    Verilog state set. For example, you may wish to convert between
    vl_logic and your own user-defined type. The vl_logic type is
    defined in the vl_types package in the pre-compiled "verilog"
    library. This library is provided in the installation directory
    along with the other pre-compiled libraries (std and ieee). The
    source code for the vl_types package can be found in the directory
    "<install_dir>/vhdl_src/verilog".

    Verilog states are mapped to std_logic and bit as follows:

        Verilog     std_logic     bit
        -------     ---------     ---
          HiZ          'Z'        '0'
          Sm0          'L'        '0'
          Sm1          'H'        '1'
          SmX          'W'        '0'
          Me0          'L'        '0'
          Me1          'H'        '1'
          MeX          'W'        '0'
          We0          'L'        '0'
          We1          'H'        '1'
          WeX          'W'        '0'
          La0          'L'        '0'
          La1          'H'        '1'
          LaX          'W'        '0'
          Pu0          'L'        '0'
          Pu1          'H'        '1'
          PuX          'W'        '0'
          St0          '0'        '0'
          St1          '1'        '1'
          StX          'X'        '0'
          Su0          '0'        '0'
          Su1          '1'        '1'
          SuX          'X'        '0'

        For Verilog states with ambiguous strength:

        	- bit receives '0'.
        	- std_logic receives 'X' if either the 0 or 1 strength
              components are greater than or equal to strong strength.
        	- std_logic receives 'W' if both the 0 and 1 strength
              components are less than strong strength.

    VHDL type bit is mapped to Verilog states as follows:

        bit     Verilog
        ---     -------
        '0'       St0
        '1'       St1

    VHDL type std_logic is mapped to Verilog states as follows:

        std_logic     Verilog
        ---------     -------
           'U'          StX
           'X'          StX
           '0'          St0
           '1'          St1
           'Z'          HiZ
           'W'          PuX
           'L'          Pu0
           'H'          Pu1
           '-'          StX

VHDL instantiation of Verilog design units
------------------------------------------

A Verilog design unit may be instantiated from VHDL if it
meets the following criteria:

    1) The design unit is a module (UDPs are not allowed).

    2) The ports are named ports (Verilog allows unnamed ports).

A Verilog module that is compiled into a library can be referenced
from a VHDL design as though the module is a VHDL entity. The
interface to the module can be extracted from the library in the form
of a component declaration by running the VGENCOMP tool. Given a
library and module name, VGENCOMP writes a component declaration to
stdout. The usage of VGENCOMP is:

Usage: vgencomp [options] <module>
Options: -lib name        Library name (default is work)
         -s               Generate std_logic port types (default)
         -b               Generate bit port types
         -v               Generate vl_logic port types

The component port types are std_logic and std_logic_vector by default.
Optionally, you can choose bit and bit_vector or vl_logic and
vl_logic_vector.

Once you have generated a component declaration for a Verilog module,
you can instantiate the component just like any other VHDL component.
In addition, you can reference a Verilog module in the entity aspect
of a component configuration - all you need to do is specify a module
name instead of an entity name. You can also specify an optional
architecture name, but it will be ignored because there is currently
no way to assign an architecture name to a Verilog module.

VGENCOMP generates a component declaration according to these rules:

Component name:

    The component name is the same as the module name. If the module
    name is not a valid VHDL identifier or if the name contains any
    upper case letters, then the component name is in the form of a
    VHDL extended identifier: \<module name>\.

	The extended identifier is a feature of VHDL 1076-1993, and you
    must enable the 1993 features when you compile any VHDL that
    contains an extended identifier (invoke VCOM with -93).

    Examples:

    Verilog module name     VHDL component name
    -------------------     -------------------
    topmod                  topmod
    TOPMOD                  \TOPMOD\
    TopMod                  \TopMod\
    top_mod                 top_mod
    _topmod                 \_topmod\

Generic clause:

    A generic clause is generated if the module has parameters.
	A corresponding generic is defined for each parameter that
    has an initial value that does not depend on any other
    parameters.

    The generic name is the same as the parameter name. If the
    parameter name is not a valid VHDL identifier, then the
    generic name is in the form of a VHDL extended identifier:
    \<parameter name>\. For user convenience, and because parameter
    names are unlikely to differ only by case, an extended
    identifier is not used to preserve case.

    The generic type is determined by the parameter's initial
    value as follows:

    Parameter value       Generic type
    ---------------       ------------
    integer               integer
    real                  real
    string literal        string

    The default value of the generic is the same as the parameter's
    initial value.

    Examples:

    Verilog parameter                VHDL generic
    -----------------                ------------
    parameter p1 = 1 - 3;            p1 : integer := -2;
    parameter p2 = 3.0;              p2 : real := 3.000000;
    parameter p3 = "Hello";          p3 : string := "Hello";

Port clause:

    A port clause is generated if the module has ports. A
    corresponding VHDL port is defined for each named port.

    The VHDL port name is the same as the Verilog port name. If the
    Verilog port name is not a valid VHDL identifier, then the
    VHDL port name is in the form of a VHDL extended identifier:
    \<port name>\. For user convenience, and because port
    names are unlikely to differ only by case, an extended
    identifier is not used to preserve case.

    The VHDL port type is selected by the user from among bit, std_logic,
    and vl_logic. If the Verilog port has a range, then the VHDL port
    type is bit_vector, std_logic_vector, or vl_logic_vector. If the
    range does not depend on parameters, then the vector type will
    be constrained accordingly, otherwise it will be unconstrained.

    Examples:

    Verilog port              VHDL port
    ------------              ---------
    input p1;                 p1 : in std_logic;
    output [7:0] p2;          p2 : out std_logic_vector(7 downto 0);
    output [4:7] p3;          p3 : out std_logic_vector(4 to 7);
    inout [width-1:0] p4;     p4 : inout std_logic_vector;

Configuration declarations are allowed to reference Verilog modules
in the entity aspects of component configurations, but the configuration
declaration cannot extend into a Verilog instance to configure the
instantiations within the Verilog module.

Verilog instantiation of VHDL design units
------------------------------------------

A VHDL design unit may be instantiated from Verilog if it
meets the following criteria:

    1) The design unit is an entity/architecture pair or a
       configuration declaration.

    2) The entity ports are of type bit, bit_vector, std_ulogic,
       std_ulogic_vector, vl_ulogic, vl_ulogic_vector, or their
       subtypes. The port clause may have any mix of these types.

    3) The generics are of type integer, real, time, physical,
       enumeration, or string. String is the only composite type
       allowed.

Reference a VHDL entity or configuration from Verilog as though the
design unit is a module of the same name (in lower case). Port
associations may be named or positional. Use the same port names and
port positions that appear in the entity. Named port associations are
*NOT* case sensitive. Generic associations are provided via the
module instance parameter value list. List the values in the same
order that the generics appear in the entity. The defparam
statement is not allowed for setting generic values.

The entity default architecture is selected from the searched
libraries (from the -L switch) unless specified otherwise.
Verilog does not have the concept of architectures or libraries,
so the escaped identifier is employed to provide an extended form
of instantiation:

	\mylib.entity(arch) u1 (a, b, c);
	\mylib.entity u1 (a, b, c);
	\entity(arch) u1 (a, b, c);

If the escaped identifier is in the form of one of the above and
it is not the name of a design unit in the searched libraries,
then the instantiation is broken down as follows:

    library = mylib
    design unit = entity
    architecture = arch
