Features • High performance, low power AVR® 8-bit Microcontroller • Advanced RISC architecture - 135 powerful instructions - most single clock cycle execution - 32 X 8 general purpose working registers - Fully static operation - Up to 16MIPS throughput at 16MHz - On-chip 2-cycle multiplier • Non-volatile program and data memories - 64/128Kbytes of in-system self-programmable flash • Endurance: 1 00,000 write/erase cycles - Optional Boot Code section with independent lock bits • USB boot loader programmed by default in the factory • In-system programming by on-chip boot program hardware activated after reset • True read-while-write operation • All supplied parts are pre-programed with a default USB bootloader - 2K/4K (64K/128K flash version) bytes EEPROM • Endurance: 1 00,000 write/erase cycles - 4K/8K (64K/128K flash version) bytes internal SRAM - Up to 64Kbytes optional external memory space - Programming lock for software security • JTAG (IEEE std. 1149.1 compliant) interface - Boundary-scan capabilities according to the JTAG standard - Extensive on-chip debug support - Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface • USB 2.0 full-speed/low-speed device and on-the-go module - Complies fully with: - Universal serial bus specification REV 2.0 - On-the-go supplement to the USB 2.0 specification rev 1.0 - Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s • USB full-speed/low speed device module with interrupt on transfer completion - Endpoint 0 for control transfers: up to 64-bytes - Six programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers - Configurable endpoints size up to 256bytes in double bank mode - Fully independent 832bytes USB DPRAM for endpoint memory allocation - Suspend/resume interrupts - Power-on reset and USB bus reset - 48MHz PLL for full-speed bus operation - USB bus disconnection on microcontroller request • USB OTG reduced host: - Supports host negotiation protocol (HNP) and session request protocol (SRP) for OTG dual-role devices - Provide status and control signals for software implementation of HNP and SRP - Provides programmable times required for HNP and SRP • Peripheral features - Two 8-bit timer/counters with separate prescaler and compare mode - Twol 6-bit timer/counter with separate prescaler, compare- and capture mode 8-bit Atmel Microcontroller with 64/128Kbytes of ISP Flash and USB Controller AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 7593L-AVR-09/12 - Real time counter with separate oscillator - Four 8-bit PWM channels - Six PWM channels with programmable resolution from 2 to 16 bits - Output compare modulator - 8-channels, 10-bit ADC - Programmable serial USART - Master/slave SPI serial interface - Byte oriented 2-wire serial interface - Programmable watchdog timer with separate on-chip oscillator - On-chip analog comparator - Interrupt and wake-up on pin change • Special microcontroller features - Power-on reset and programmable brown-out detection - Internal calibrated oscillator - External and internal interrupt sources - Six sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby • I/O and packages - 48 programmable I/O lines - 64-lead TQFP and 64-lead QFN • Operating voltages - 2.7 - 5.5V • Operating temperature - Industrial (-40°C to +85'’C) • Maximum frequency - 8MHz at 2.7V - industrial range - 16MHz at 4.5V - industrial range 2 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 1. Pin configurations Figure 1 -1 . Pinout Atmel AT90USB64/1 28-TQFP. o o Q Z C3 CO o o Q Q t: O 1 — CVJ CO LO CD N. o o O O o O o o o C\J Q Q Q Q Q Q Q Q Q Q Q LL < < < < < < < < < LU O y- C\J CO LO CD Q o O C\J DC LL LL LL LL LL LL LL LL Z o < < < < □. □. □. □. D. CL CL D. o > d; (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 UVcc D- D+ UGnd UCap VBus (lUID) PE3 (SS/PCINTO) PBO (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PBS (PCINT6/OC.1B) PB6 h' m CL o d O o d O LU CL O CO LO LU CL O CO LO o Q o z > CD C\J X X o Q CL O OT m o o O Q CL Q M m (\j o O CM Q 0. Q X oc CO Q CL Q X H D 0. 0. O IT) Q CL X o X CD Q CL 1^ Q CL O CL PA3 (AD3) PA4 (AD4) PAS (ADS) PA6 (AD6) PA7 (AD7) PE2 (ALE/HWB) PC7 (A1S/IC.3/CLK0) PCS (A14/OC.3A) PCS (A13/OC.3B) PC4 (A12/OC.3C) PC3 (A11AT.3) PC2 (A10) PC1 (A9) PCO (A8) PE1 (RD) PEG (WR) ^iniEL 7593L-AVR-09/12 Figure 1-2. Pinout Atmel AT90USB64/128-QFN. (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 UVcc D- D+ UGnd UCap VBus (lUID) PE3 (SS/PCINTO) PBO (PCINT1/SCLK) PB1 (PDI/PCINT2/l\/IOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PBS (PCINT6/OC.1B) PB6 CO o o 2 Q O t; t; t; tz O CM CO lO CO O o O O o O O o o CM Q Q CD Q Q Q Q CD D a CD Q LL < < < < < < < < < < < O Q LU o CM CO lO CD Q O o CM > "Z. QC u. U. LL LL U. u. U. LL Z O < < < < CD < CL CL CL 0. Q. CL CL CL CD > CL CL CL PA3 (AD3) PA4 (AD4) PAS (ADS) PA6 (AD6) PA7 (AD7) PE2 (ALE/HWB) PC7 (A1S/IC.3/CLKO) PCS (A14/OC.3A) PCS (A13/OC.3B) PC4 (A12/OC.3C) PC3 (A1 171.3) PC2 (A1 0) PCI (A9) PCO (A8) PEI (RD) PEG (WR) O D. Note: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 4 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 2. Overview The Atmel® AVR® AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the Atmel® AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90USB64/128 achieves throughputs approaching 1MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. ^iniEL 7593L-AVR-09/12 5 2.1 Block diagram Figure 2-1 . Block diagram. PE7 - PEO PB7 - PBO PD7-PD0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting 6 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The Atmel AT90USB64/128 provides the following features: 64/128Kbytes of In-System Pro- grammable Flash with Read-While-Write capabilities, 2K/4Kbytes EEPROM, 4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers. Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte ori- ented 2-wire Serial Interface, a 8-channels, 10-blt ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149. 1 compliant JTAG test interface, also used for accessing the On-chip Debug sys- tem and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, dis- abling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O mod- ules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using the Atmel high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot pro- gram running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB64/128 AVR is supported with a full suite of program and system development tools Including: C compilers, macro assemblers, program debugger/simulators. In-circuit emula- tors, and evaluation kits. 7593L-AVR-09/12 7 2.2 Pin descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 Port A (PA7..PA0) Port A is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the Atmel AT90USB64/128 as listed on page 78. 2.2.5 Port B (PB7..PB0) Port B is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the AT90USB64/128 as listed on page 79. 2.2.6 Port C (PC7..PC0) Port C is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs. Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the AT90USB64/128 as listed on page 82. 2.2.7 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90USB64/128 as listed on page 83. 8 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 2.2.8 Port E {PE7..PE0) Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current If the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90USB64/128 as listed on page 86. 2.2.9 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bidirectional I/O port, If the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both high sink and source capability. As inputs. Port F pins that are externally pulled low will source current If the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock Is not running. If the JTAG Interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.2.10 D- USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22Q resistor. 2.2.11 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB Dh- connector pin with a serial 22Q resistor. 2.2.12 UGND USB Pads Ground. 2.2.13 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.14 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac- itor (IpF). 2.2.15 VBUS USB VBUS monitor and OTG negociations. 2.2.16 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page 58. Shorter pulses are not guaranteed to generate a reset. 2.2.17 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 7593L-AVR-09/12 9 2.2.18 XTAL2 Output from the inverting oscillator amplifier. 2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to Vqq, even if the ADC is not used. If the ADC is used, it should be connected to Vqq through a low-pass filter. 2.2.20 AREF This is the analog reference pin for the A/D Converter. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. These code examples assume that the part specific header file is included before compilation. For I/C registers located in extended I/C map, "IN", "CUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/C. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 10 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 5. AVR CPU core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural overview Figure 5-1 . Block diagram of the AVR architecture. In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory. ^rniEL IB 7593L-AVR-09/12 11 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed In the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-blt word for- mat. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All Interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi- tion. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel AT90USB64/1 28 has Extended I/O space from 0x60 - OxFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5.3 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction set summary” on page 423 for a detailed description. 12 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 5.4 Status register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated com- pare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR status register - SREG - is defined as: Bit 7 6 5 4 3 2 1 0 r — T H S V N Z c n Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 • Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The l-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The l-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction set summary” on page 423 for detailed information. • Bit4-S: Sign Bit, S = N©V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction set summary” on page 423 for detailed information. • Bit 3 - V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction set summary” on page 423 for detailed information. • Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. • Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. 7593L-AVR-09/12 13 • Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. 5.5 General purpose register file The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 5-2. AVR CPU general purpose working registers. General purpose working registers RO R1 R2 R13 R14 R15 R16 R17 R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 OxOD OxOE OxOF 0x10 0x11 0x1 A X-register Low byte 0x1 B X-register High byte 0x1 C Y-register Low byte 0x1 D Y-register High byte 0x1 E Z-register Low byte 0x1 F Z-register High byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 5-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 5.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3. 14 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 5-3. The X-, Y-, and Z-registers. 15 XH XL 0 X-register n 0 1 R27 (0x1 B) R26 (0x1 A) 15 YH YL 0 Y-register n rp 0 1 R29 (0x1 D) R28 (0x1 C) 15 ZH ZL 0 Z-register n 0 T 0 1 R31 (0x1 F) R30 (0x1 E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine cails. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca- tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some impiementa- tions of the AVR architecture is so smail that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO 7 6 5 4 3 2 1 0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 7593L-AVR-09/12 15 5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 1 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZO I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 5-4. Note that LPM is not affected by the RAMPZ setting. Figure 5-4. The Z-pointer used by ELPM and SPM. Bit (individually) 7 0 7 0 7 I RAMPZ I ZH I ZL Bit (Z-pointer) 23 16 15 8 7 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 5.7 Instruction execution timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkcp^, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-5. The parallel instruction fetches and instruction executions. T1 T2 T3 elk CPU 1st instruction fetch < 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch > < > c T4 > c Figure 5-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destina- tion register. 16 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 5-6. Single cycle ALU operation. clkcpu Total execution time Register operands fetch ALU operation execute Result write back T1 A ( C T2 T3 T4 / \ t \ 5.8 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory program- ming” on page 359 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INTO - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 68 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory programming” on page 359. When an interrupt occurs, the Global Interrupt Enable l-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the l-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The l-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. 7593L-AVR-09/12 17 Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI Instruction, even if it occurs simultaneously with the CLI Instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly code example in rl6, SREG ; store SREG value cli ; disable interrupts during timed sequence sbiEECR, EEMPE ; Start EEPROM write SbiEECR, EEPE out SREG, rl6 ; restore SREG value (I-bit) C code example char cSREG; cSREG = SREG; /* Store SREG value */ /* disable interrupts during timed sequence */ disable_interrupt ( ) ; EECR 1= (1«EEMPE); /* Start EEPROM write */ EECR 1= (1«EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending Interrupts, as shown In this example. AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Assembly code example sei ; set Global Interrupt Enable sleep/ enter sleep, waiting- for interrupt ; note: will enter sleep before any pending ; interrupt (s) C code example enable_interrupt ( ) ; /* set Global Interrupt Enable */ sleepO; /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt (s) */ 5.8.1 Interrupt response time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is exe- cuted. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe- cution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (two bytes) Is popped back from the Stack, the Stack Pointer is incre- mented by two, and the l-bit in SREG is set. ^iniEL 7593L-AVR-09/12 19 6. Atmel AVR AT90USB64/128 memories This section describes the different memories in the AT90USB64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 6-1 . Memory mapping. Memory Mnemonic AT90USB64 AT90USB128 Flash Size Flash size 64Kbytes 128K bytes Start address 0x00000 End address Flash end OxOFFFF (1) 0X7FFF <"> OxIFFFF (1) OxFFFF 32 registers Size 32bytes Start address 0x0000 End address 0x001 F I/O registers Size 64 bytes Start address 0x0020 End address OxOOSF Ext I/O registers Size 1 60bytes Start address 0x0060 End address OxOOFF Internal SRAM Size ISRAM size 4Kbytes SKbytes Start address ISRAM start 0x0100 End address ISRAM end 0x1 OFF 0x20FF External Memory Size XMem size 0-64Kbytes Start address XMem start 0x1100 0x2100 End address XMem end OxFFFF EEPROM Size E2 size 2Kbytes 4 Kbytes Start address 0x0000 End address E2 end 0x07FF OxOFFF Notes: 1 . Byte address. 2. Word (16-bit) address. 6.1 In-system re-programmable flash program memory The AT90USB64/128 contains 128Kbytes On-chip In-System Re-programmable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K X 16. For software security, the Flash Program memory space is divided into two sections. Boot Program section and Application Program section. The Flash memory has an endurance of at least 100,000 write/erase cycles. The AT90USB64/128 Program Counter (PC) is 16 bits wide, thus addressing the 128K program memory locations. The operation of Boot Program section and associated Boot Lock bits for 20 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 software protection are described in detail in “Memory programming” on page 359. “Memory pro- gramming” on page 359 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface. Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction execution tim- ing” on page 16. Figure 6-1. Program memory map. Program memory 0x00000 Flash end 6.2 SRAM data memory Figure 6-2 shows how the Atmel AT90USB64/128 SRAM memory is organized. The AT90LISB64/128 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used. The first 4,352/8,448 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 4,096/8,192 locations address the internal data SRAM. ^iniEL 7593L-AVR-09/12 21 An optional external data SRAM can be used with the Atmel AT90USB64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,352/8,448 bytes, so when using 64KB (65,536 bytes) of External Memory, 61,184/57,088 Bytes of External Memory are available. See “External memory interface” on page 31 for details on how to take advantage of the external memory map. When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PEO and PEI) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register. Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine cails and returns take three clock cycles extra because the three-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe- line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the Instruction set Manual for one, two, and three wait-states. The five different addressing modes for the data memory cover: Direct, Indirect with Displace- ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 8,192 bytes of internal data SRAM in the AT90USB64/128 are all accessible through all these addressing modes. The Reg- ister File is described in “General purpose register file” on page 14. 22 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 6-2. Data memory map. Data memory $0000 - $001 F $0020 - $005F $0060 - $00FF I SRAM start ISRAM end XMem start $FFFF 6.2.1 Data memory access times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk^py cycles as described in Figure 6-3. ^iniEL 7593L-AVR-09/12 23 Figure 6-3. On-chip data SRAM access cycles. T1 T2 ^"^CPU Address Data WR Data RD \ t \ t V Compute address )( Address valid c T3 Memory access instruction Next instruction 6.3 EEPROM data memory The Atmel AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 373, page 377, and page 362 respectively. 6.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 6-3. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instruc- tions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, Vqq is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM corruption” on page 29. for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 24 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 6.3.2 EEARH and EEARL - The EEPROM Address Register Bit 15 14 13 12 11 10 9 8 - - - - EEAR11 EEAR10 EEAR9 EEAR8 EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEARO 7 6 5 4 3 2 1 0 Read/write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 X X X X X X X X X X X X EEARH EEARL • Bits 15. .12 - Res: Reserved bits These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero. • Bits 1 1 ..0 - EEAR8..0: EEPROM address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 6.3.3 EEDR - The EEPROM Data Register Bit Read/write Initial value 7 6 5 4 3 2 1 I MSB I I I I I I R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 LSB R/W 0 ] EEDR • Bits 7..0 - EEDR7.0: EEPROM data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 6.3.4 EECR - The EEPROM Controi Register Bit 7 6 5 4 3 2 1 0 F - EEPM1 EEPMO EERIE EEMPE EEPE EERE 1 Read/write R R R/W R/W R/W R/W R/W R/W Initial value 0 0 X X 0 0 X 0 • Bits 7..6 - Res: Reserved bits These bits are reserved bits in the AT90USB64/128 and will always read as zero. • Bits 5, 4 - EEPM1 and EEPMO: EEPROM Programming Mode bits The EEPROM Programming Mode bit setting defines which programming action that will be trig- gered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 6-2 on page 26. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to ObOO unless the EEPROM is busy programming. 7593L-AVR-09/12 25 Table 6-2. EEPROM Mode bits. EEPM1 EEPMO Programming time Operation 0 0 3.4ms Erase and Write in one operation (atomic operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 - Reserved for future use • Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEPE is cleared. • Bit 2 - EEMPE: EEPROM Master Programming Enable The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure. • Bit 1 - EEPE: EEPROM Programming Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other- wise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1 . Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory pro- gramming” on page 359 for details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. 26 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is haited for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Osciilator is used to time the EEPROM accesses. Table 6-3 lists the typical pro- gramming time for EEPROM access from the CPU. Table 6-3. EEPROM programming time. Symbol Number of calibrated RC oscillator cycles Typical programming time EEPROM write (from CPU) 26,368 3.3ms The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 7593L-AVR-09/12 27 Assembly code example EEPROM_write : ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (rl8 : rl7) in address register out EEARH, rl8 out EEARL, rl7 ; Write data (rl6) to Data Register out EEDR,rl6 / Write logical one to EEMPE sbi EECR, EEMPE / start eeprom write by setting EEPE sbi EECR, EEPE ret C code example void EEPROM_write (unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1«EEPE)) /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = UCData; /* Write logical one to EEMPE */ EECR 1= (1«EEMPE); /* Start eeprom write by setting EEPE */ EECR 1= (1«EEPE); Note: 1 . See “About code examples” on page 1 0. 28 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly code example EEPROM_read : ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (rl8 : rl7 ) in address register out EEARH, rl8 out EEARL, rl7 ; Start eeprom read by wri ting EERE Sbi EECR,EERE / Read data from Data Register in rl6,EEDR ret C code example unsigned char EEPROM_read (unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1«EEPE)) /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1«EERE); /* Return data from Data Register */ return EEDR; } Note: 1 . See “About code examples” on page 10. 6.3.5 Preventing EEPROM corruption During periods of low Vqq the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec- ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low Vqq reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. 7593L-AVR-09/12 29 6.4 I/O memory The I/O space definition of the Atmel AT90USB64/128 is shown in “Register summary” on page 419. All AT90USB64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1 F are directly bit-accessible using the SBI and OBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90USB64/128 is a compiex microcontrolier with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - OxFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the OBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The OBI and SBI instructions work with reg- isters 0x00 to 0x1 F only. The I/O and peripherals control registers are explained in later sections. 6.4.1 General purpose I/O registers The AT90USB64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1 F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 6.4.2 GPIOR2 - General purpose I/O Register 2 Bit 7 6 5 4 3 2 1 0 LSB 1 GPIOR2 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 GPIOR1 - General purpose I/O Register 1 Bit 7 6 5 4 3 2 1 0 LSB 1 GPIOR1 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 GPIORO - General purpose I/O Register 0 Bit 7 6 5 4 3 2 1 0 LSB I GPIORO Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 30 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 6.5 External memory interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD- display, A/D, and D/A. The main features are: • Four different wait-state settings (inciuding no wait-state) • Independent wait-state setting for different externai Memory sectors (configurabie sector size) • The number of bits dedicated to address high byte is seiectabie • Bus keepers on data iines to minimize current consumption (optionai) 6.5.1 Overview When the external MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated External Memory pins (see Figure 2-1 on page 6, Table 11-3 on page 78, and Table 1 1-9 on page 82). The memory configuration is shown in Figure 6-4. Figure 6-4. External memory with sector select. Memory configuration A 0x0000 ISRAM end XMem start |sRL[2..0] OxFFFF External memory (0-60K X 8) Internal memory Lower sector SRW01 SRWOO Upper sector SRW11 SRW10 6.5.2 Using the externai memory interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus • A15:8: High-order address bus (configurable number of bits) • ALE: Address latch enable • RD: Read strobe • WR: Write strobe The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A - XMCRA, and the External Memory Control Register B - XMCRB. ^IrniU 7593L-AVR-09/12 ® When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “l/O-ports” on page 71 . The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Fig- ure 6-6 on page 33 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address, data and ALE ports, but the RD and WR strobes will not toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 6-5 illustrates how to connect an external SRAM to the AVR using an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high. 6.5.3 Address latch requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi- tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The External Memory Interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are: • D to Q propagation delay (tp^) • Data setup time before G low (tgy) • Data (address) hold time after G low (jh) The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of t^, = 5ns. Refer to tu^xx ld/^llaxx st “External data memory timing” Tables 31-7 through Tables 31-13 on pages 399 - 401. The D-to-Q propagation delay (tp^) must be taken into consideration when calculating the access time requirement of the external component. The data setup time before G low (tgy) must not exceed address valid to ALE low (tAVLLc) minus RGB wiring delay (dependent on the capacitive load). Figure 6-5. External SRAM connected to the AVR. 32 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 6.5.4 Pull-up and bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis- abled and enabled in software as described in “XMCRB - External Memory Control Register B” on page 36. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while these lines are tri-stated by the XMEM interface. 6.5.5 Timing External Memory devices have different timing requirements. To meet these requirements, the XMEM interface provides four different wait-states as shown in Table 6-5 on page 36. It is impor- tant to consider the timing specification of the External Memory device before selecting the wait- state. The most important parameters are the access time for the external memory compared to the setup requirement. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (see tLLpL-n tRLpu., - tovRn in Tables 31-6 through Tables 31-13 on pages 399 - 401). The different wait-states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings. This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Tables 31-6 through Tables 31-13 and Figure 31-7 to Figure 31-10 in the “External data memory timing” on page 399. Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse- quently, the XMEM interface is not suited for synchronous operation. Figure 6-6. External data memory cycles without wait-state (SRWn1=0 and SRWn0=0). System Clock (CLKQpy) ALE 1 T1 1 T2 I T3 1 T4 1 ^ v_ Jf \ / \ \ r 1 1 1 1 i r ; \ i i / i 1 1 1 1 - A15:8 Pr^v. addr. 'V A ' Address | X 1 1 1 1 DA7:0 Pr^v. data ;X Address ' Data ; X 1 1 1 1 WR ^ ^ :/ r_ 1 1 1 1 1 1 1 1 — DA7:0 (XMBK = 0) Pr^v. data X Address ) \ ; ) T 1 1 1 DA7:0 (XMBK= 1) Pr4v. data X Address \ X i X ; 1 1 1 1 ■rd 1 1 \ \ 1 1 i tr 7593L-AVR-09/12 33 Note: 1. SRWnt =SRW11 (upper sector) or SRW01 (lower sector), SRWnO = SRW10 (upper sector) or SRWOO (lower sector). The ALE pulse In period T4 is only present if the next instruction accesses the RAM (internal or external). Figure 6-7. External data memory cycles with SRWnt = 0 and SRWnO = 1 System clock (CLKqpu) ALE I T1 1 t2 ; T3 1 T4 1 1 T5 't \ \ r r \ / \ 1 1 1 1 1 / i \ i / ; 1 A15:8 Pr^v. addr. iX i Address | 1 X I 1 1 DA7:0 Pr^v. data ;X Address XxxX 1 Data 1 1 X i 1 1 1 WR i 1 1 1 i - DA7:0 (XMBK = 0) Pr^v. data iX Address ) 1 — y- 1 DA7:0 (XMBK = 1) Pr^v. data iX Address | X Data 1 1 1 X i 1 1 1 ' 1 1 :/ I 1 1 ^ Note: 1. SRWnt =SRWtt (upper sector) or SRWOt (lower sector), SRWnO = SRWtO (upper sector) or SRWOO (lower sector). The ALE pulse In period T5 is only present if the next instruction accesses the RAM (internal or external). Figure 6-8. External data memory cycles with SRWnt = t and SRWnO = 0 Tt T2 I T3 I T4 TS T6 \ em clock (CLK Qpj) jf / / \ 'r \ r \ \ T ALE ; j \ \ / \ A15:8 Pr^v. addr. \ Address | ' ' ' : DA7:0 Pr4v. data nx Address i ^ x_ i wr ; |\ L - DA7:0 (XMBK = 0) Pr^v. data iX Address ) | Data | y He I : : : ■D DA7:0 (XMBK = 1 ) Pr^v. data Address \ ^ Data \ cc ; \ : 7 I I ^ Note: t. SRWnt =SRWtt (upper sector) or SRWOt (lower sector), SRWnO = SRWtO (upper sector) or SRWOO (lower sector). The ALE pulse In period T6 is only present if the next instruction accesses the RAM (internal or external). AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 6-9. External data memory cycles with SRWnt = 1 and SRWnO = 1 I T1 I T2 ! T3 I T4 ] T5 System clock {CLK^py) I A15:8 Pr^v. addr. DA7:0 Pr^v. data DA7:0(XMBK = 0) Pr^v.dala Address 3-^ DA7:0(XMBK=1) Pr^v.data ■V Address XXX] K: X X X X X X Note: 1. SRWnI =SRW11 (upper sector) or SRW01 (lower sector), SRWnO = SRW10 (upper sector) or SRWOO (lower sector). The ALE pulse In period T7 is only present if the next instruction accesses the RAM (internal or external). 6.5.6 XMCRA - External Memory Control Register A Bit 7 6 5 4 3 2 1 0 1 SRE SRL2 SRL1 SRLO SRW11 SRW10 SRW01 SRWOO I Read/write R/W R/W R/W RAW RAW RAW RAW RAW Initial value 0 0 0 0 0 0 0 0 XMCRA • Bit 7 - SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface. The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used. • Bit 6..4 - SRL2:0: Wait-state Sector Limit It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1 , and SRLO bits select the split of the sectors, see Table 6-4 on page 36 and Figure 6-4 on page 31 . By default, the SRL2, SRL1 , and SRLO bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW1 1 and SRW10 bits. 7593L-AVR-09/12 35 Table 6-4. Sector limits with different settings of SRL2..0. SRL2 SRL1 SRLO Sector limits 0 0 X Lower sector = N/A Upper sector = 0x21 00 - OxFFFF 0 1 0 Lower sector = 0x2100 - 0x3FFF Upper sector = 0x4000 - OxFFFF 0 1 1 Lower sector = 0x2100 - 0x5FFF Upper sector = 0x6000 - OxFFFF 1 0 0 Lower sector = 0x2100 - 0x7FFF Upper sector = 0x8000 - OxFFFF 1 0 1 Lower sector = 0x2100 - 0x9FFF Upper sector = OxAOOO - OxFFFF 1 1 0 Lower sector = 0x21 00 - OxBFFF Upper sector = OxCOOO - OxFFFF 1 1 1 Lower sector = 0x2100 - OxDFFF Upper sector = OxEOOO - OxFFFF • Bit 3. .2 - SRW1 1 , SRW10: Wait-state Select bits for upper sector The SRW1 1 and SRW10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see Table 6-5. • Bit 1 ..0 - SRW01 , SRWOO: Wait-state Select bits for lower sector The SRW01 and SRWOO bits control the number of wait-states for the lower sector of the exter- nal memory address space, see Table 6-5. Table 6-5. Wait states SRWnI SRWnO Wait states 0 0 No wait-states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address Note: 1 . n = 0 or 1 (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figures 6-6 through Figures 6-9 on page 33 to page 35 for how the setting of the SRW bits affects the timing. XMCRB - External Memory Control Register B Bit 7 6 5 4 3 2 1 0 1 XMBK - - - - XMM2 XMMI XMMO ] XMCRB Read/write R/W R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 • Bit 7- XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri- AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one. • Bit 6..3 - Res: Reserved Bits These bits are reserved and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. • Bit 2..0 - XMM2, XMM1 , XMMO: Externai Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 6-6. As described in “Using all 64KB locations of external memory” on page 38, it is possible to use the XMMn bits to access all 64KB locations of the External Memory. Table 6-6. Port C pins released as normal port pins when the external memory is enabled. XMM2 XMM1 XMMO # bits for external memory address Released port pins 0 0 0 8 (full 56KB space) None 0 0 1 7 PC7 0 1 0 6 PC7 - PC6 0 1 1 5 PC7 - PC5 1 0 0 4 PC7 - PC4 1 0 1 3 PC7 - PC3 1 1 0 2 PC7 - PC2 1 1 1 No address high bits Full Port C 6.5.8 Using all locations of external memory smaller than 64KB Since the external memory is mapped after the internal memory as shown in Figure 6-4 on page 31, the external memory is not addressed when addressing the first 8,448/4,352 bytes (128/64Kbytes version) of data space. It may appear that the first 8,448/4,352 bytes of the exter- nal memory are inaccessible (external memory addresses 0x0000 to 0x1 OFF or 0x0000 to 0x20FF). However, when connecting an external memory smaller than 64KB, for example 32KB, these locations are easily accessed simply by addressing from address 0x8000 to OxAIFF. Since the External Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to OxAl FF will appear as addresses 0x0000 to 0x21 FF for the external memory. Addressing above address OxAIFF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application soft- ware, the external 32KB memory will appear as one linear 32KB address space from 0x2200 to OxAIFF. This is illustrated in Figure 6-10 on page 38. 7593L-AVR-09/12 37 Figure 6-10. Address map with 32KB external memory. Memory configuration A AVR memoiy map External 32K SRAM 0x0000 Internal memory 0X0000 0X20FF ISRAM end 0x2100 XMem start 0X7FFF External 0x7FFF 0x8000 memory ISRAM end + 0x8000 XMem start + 0x8000 (Unused) OxFFFF Using aii 64KB iocations of externai memory Since the External Memory is mapped after the Internal Memory as shown in Figure 6-4, only 56KB of External Memory is available by default (address space 0x0000 to 0x20FF is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releas- ing the most significant bits for normal Port Pin operation, the Memory Interface will address 0x0000 - 0x2FFF. See the following code examples. Care must be exercised using this option as most of the memory is masked away. AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Assembly code example ; OFFSET is defined to 0x4000 to ensure ; external memory access ; Configure Port C (address high byte) to ; output 0x00 when the pins are released ; for normal Port Pin operation Idi rl6, OxFF out DDRC, rl6 Idi rl6, 0x00 out PORTC, rl6 ; release PC7 : 6 Idi rl6, (1< 1 00 7593L-AVR-09/12 43 Table 7-4. Start-up times for the low power crystal oscillator clock selection. (Continued) Oscillator source/ power conditions Start-up time from power-down and power-save Additional delay from reset (Vcc = 5.0V) CKSELO SUT1..0 Crystal Oscillator, BOD enabled 16KCK 14CK 1 01 Crystal Oscillator, fast rising power 16KCK 14CK + 4.1ms 1 10 Crystal Oscillator, slowly rising power 16KCK 14CK-r 65ms 1 11 Notes: 1 . These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. Table 7-5. Start-up times for the internal calibrated RC oscillator clock selection. Power conditions Start-up time from power- down and power-save Additional delay from reset (Vcc = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK - 1 - 4.1ms 01 Slowly rising power 6CK 14CK-H65ms 10 Reserved 11 Note: 1. The device is shipped with this option selected. 7.4 Low frequency crystal oscillator The device can utilize a 32.768kHz watch crystal as clock source by a dedicated low frequency crystal oscillator. The crystal should be connected as shown in Figure 7-2 on page 43. When this Oscillator is selected, start-up times are determined by the SUT Fuses and CKSELO as shown in Table 7-6. Table 7-6. Start-up times for the low frequency crystal oscillator clock selection. Power conditions Start-up time from power-down and power-save Additional delay from reset (Vcc = 5.0V) CKSELO SUT1..0 BOD enabled 1KCK 14CK<^) 0 00 Fast rising power 1KCK 14CK + 4.1ms 0 01 Slowly rising power 1KCK 14CK + 65ms 0 10 Reserved 0 11 BOD enabled 32KCK 14CK 1 00 Fast rising power 32KCK 14CK + 4.1ms 1 01 Slowly rising power 32KCK 14CK-r 65ms 1 10 Reserved 1 11 44 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Note: 1 . These options should only be used if frequency stabiiity at start-up is not important for the application. 7.5 Calibrated internal RC oscillator The calibrated internal RC oscillator by default provides a 8.0MHz clock. The frequency is nomi- nal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System clock prescaler” on page 47 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 7-7. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC oscillator. At 3V and 25°C, this calibration gives a frequency of 8MHz ±10%. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within ±10% accuracy, by changing the OSCCAL register. When this oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see Section “Calibration byte” on page 362 Table 7-7. Internal calibrated RC oscillator operating modes ^''**^*. Frequency range [MHz] CKSEL3..0 CO CO 0010 Notes: 1 . The device is shipped with this option selected. 2. The frequency ranges are preliminary values. Actual values are TBD. 3. If 8MHz frequency exceeds the specification of the device (depends on Vqq), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. When this oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7-5 on page 44. Table 7-8. Start-up times for the internal calibrated RC oscillator clock selection. Power conditions Start-up time from power- down and power-save Additionai delay from reset (Vgc = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK±65ms 10 Reserved 11 Note: 1 . The device is shipped with this option selected. 7.5.1 OSCCAL - Oscillator Calibration Register Bit 7 6 5 4 3 2 1 0 1 CAL7 CAL6 CALS CAL4 CALS CAL2 CAL1 CALO 1 Read/write RAN RAN RAN RAN RAN RAN R/W RAN 1 OSCCAL Initial value Device specific calibration value • Bits 7..0 - CAL7..0: Oscillator calibration value The Oscillator Calibration Register is used to trim the calibrated internal RC oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0MHz at 25°C. The application software can write this register to change the oscillator frequency. The oscillator can 7593L-AVR-09/12 45 be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±10% accuracy. Calibration out- side that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre- quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre- quency range 7.3 - 8.1 MHz. 7.6 External clock The device can utilize a external clock source as shown in Figure 7-3. To run the device on an external clock, the CKSEL fuses must be programmed as shown in Table 7-1 on page 41 . Figure 7-3. External clock drive configuration. NC XTAL2 EXTERNAL CLOCK XTAL1 SIGNAL GND When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 7-9. Table 7-9. Start-up times for the external clock selection. Power conditions Start-up time from power- down and power-save Additional delay from reset (V^c = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK + 65ms 10 Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes. 46 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System clock prescaler” on page 47 for details. 7.7 Clock output buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir- cuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output. 7.8 Timer/counter oscillator The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter- nal clock source. See Figure 7-2 on page 43 for crystal connection. Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to logic one. See “Asynchronous operation of the Timer/Counter” on page 161 for further descrip- tion on selecting external clock as input instead of a 32kHz crystal. 7.9 System clock prescaler The Atmel AT90USB64/128 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR - Clock Prescale Register” on page 48. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk|/o, clk,a,Dc> clkcpu, and clkpL^s^sH are divided by a factor as shown in Table 7-10 on page 48. When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corre- sponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ- ten, it takes between T1 h- T2 and T1 h- 2 x T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1 . Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 7593L-AVR-09/12 47 7.9.1 CLKPR - Clock Prescale Register Bit 7 6 5 4 3 2 1 0 1 CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPSO Read/write R/W R R R R/W R/W R/W R/W Initial value 0 0 0 0 See bit description CLKPR • Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this timeout period does neither extend the timeout period, nor clear the CLK- PCE bit. • Bits 3..0 - CLKPS3..0: Clock Prescaler Select Bits 3-0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock Input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 7-10. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used If the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 fuse programmed. Table 7-10. Clock prescaler select. CLKPS3 CLKPS2 CLKPS1 CLKPSO Clock division factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 48 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 CLKPS3 CLKPS2 CLKPS1 CLKPSO Clock division factor 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved 7.10 PLL The PLL is used to generate internal high frequency (48MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1). The internal RC oscillator can not be used for USB operations. 7.10.1 Internal PLL for USB interface The internal PLL in Atmel AT90USB64/128 generates a clock frequency that is 24x multiplied from nominally 2MHz input. The source of the 2MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 2MHz (see Section 7.10.2 for PLL interface). Figure 7-4. PLL clocking system. PILE PLOCK 7.10.2 PLLCSR - PLL Control and Status Register Bit 7 6 5 4 3 2 1 0 $29 ($29) 1 1 PLLP2 PLLP1 PLLPO PLLE PLOCK 1 PLLCSR Read/write R R R RAW RAW RAW RAW R/W Initial value 0 0 0 0 0 0 0/1 0 • Bit 7..5 - Res: Reserved bits These bits are reserved bits in the AT90USB64/128 and always read as zero. • Bit 4..2 - PLLP2:0 PLL prescaler These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the PLL. ^iniEL 7593L-AVR-09/12 49 Table 7-1 1 . PLL input prescaler configurations. PLLP2 PLLP1 PLLPO Clock division factor External XTAL required for USB operation [MHz] 0 0 0 Reserved - 0 0 1 Reserved - 0 1 0 Reserved - 0 1 1 4 8 1 0 0 Reserved - 1 0 1 8(1) 16<^> 1 1 0 8(2) 16<2) 1 1 1 Reserved - Note: 1 . For Atmel AT90USB128x only. Do not use with Atmel AT90USB64x. 2. For AT90USB64X only. Do not use with AT90USB128x. • Bit 1 - PLLE: PLL Enable When the PLLE is set, the PLL is started. • Bit 0 - PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it takes about 1 00ms for the PLL to lock. To clear PLOCK, clear PLLE and PLLPx bits. AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 8. Power management and sleep modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1 , and SMO bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 8-1 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 7-1 on page 40 presents the different clock systems in the Atmel AT90USB64/128, and their distribution. The figure is helpful in selecting an appropriate sleep mode. 8.0.1 SMCR - Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 - - - SM2 SM1 SMO SE 1 Read/write R R R R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 "I SMCR • Bits 3, 2, 1 - SM2..0: Sleep Mode Select Bits 2, 1 , and 0 These bits select between the six available sleep modes as shown in Table 8-1 . Table 8-1 . Sleep mode select. SM2 SMI SMO Sleep mode 0 0 0 Idle 0 0 1 ADC noise reduction 0 1 0 Power-down 0 1 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby 1 1 1 Extended Standby Note: 1 . Standby modes are only recommended for use with external crystals or resonators. • Bit 1 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 7593L-AVR-09/12 51 8.1 Idle mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkQpy and clkpLys^gp, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati- cally when this mode is entered. 8.2 ADC noise reduction mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkl/0, clkCPU, and clkFLASH, while allowing the other clocks to run (including clkUSB). This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabied, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU from ADC Noise Reduction mode. 8.3 Power-down mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, whiie the external interrupts, the 2- wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on INT7:4, an external interrupt on INT3:0, a pin change interrupt or an asynchronous USB interrupt sources (VBUSTI, WAKEUPI, IDTI and HWUPI), can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External interrupts” on page 92 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Ciock sources” on page 41 . 8.4 Power-save mode When the SM2..0 bits are written to 01 1, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: 52 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2. 8.5 Standby mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MOD enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Note that in Stanby mode the PLL is disabled and the USB interface will not function. 8.6 Extended Standby mode When the SM2..0 bits are 1 1 1 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. Table 8-2. Active clock domains and wake-up sources in the different sleep modes. Active clock domains Oscillators Wake-up sources Sleep mode 3 Q. U o I (A < li. o o o u Q < o >- CO < o Main clock source enabled Timer oscillator enabled INT7:0 and Pin Change TWI address match Timer2 SPM/ EEPROM ready ADC WDT interrupt Other I/O USB synchronous interrupts USB asynchonous interrupts Idle X X X X X(2) X X X X X X X X X ADCNRM X X X X(2) X(3) X X(2) X X X X X Power-down X(3) X X X Power-save X X(2) X(3) X X X X Standby X X(3) X X X Extended standby X(2) X X(2) X(3) X X X X Notes: 1 . Only recommended with external crystal or resonator selected as clock source. 2. If Tlmer/Counter2 is running in asynchronous mode. 3. For INT7:4, only level interrupt. 4. Asynchronous USB interrupts are VBUSTI, WAKEUPI, IDTI and HWUPI. 7593L-AVR-09/12 53 8.7 Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher- als to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should In most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. 8.7.1 PRRO - Power Reduction Register 0 Bit 7 6 5 4 3 2 1 0 1 PRTWI PRTIM2 PRTIMO - PRTIM1 PRSPI - PRADC 1 Read/write RAW RAW RAW R RAW RAW R RAW Initial value 0 0 0 0 0 0 0 0 PRRO • Bit 7 - PRTWi: Power Reduction TWi Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. • Bit 6 - PRTiM2: Power Reduction Timer/Counter2 Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown. • Bit 5 - PRTiMO: Power Reduction Timer/CounterO Writing a logic one to this bit shuts down the Timer/CounterO module. When the Timer/CounterO is enabled, operation will continue like before the shutdown. • Bit 4 - Res: Reserved bit This bit is reserved and will always read as zero. • Bit 3 - PRTiMI : Power Reduction Timer/Counterl Writing a logic one to this bit shuts down the Timer/Counterl module. When the Timer/Counterl is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPi: Power Reduction Seriai Peripherai interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. • Bit 1 - Res: Reserved bit These bits are reserved and will always read as zero. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 54 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 8.7.2 PRR1 - Power Reduction Register 1 Bit 7 6 5 4 3 2 1 0 1 PRUSB - - - PRTIM3 - - PRUSART1 Read/write R/W R R R R/W R R R/W Initial value 0 0 0 0 0 0 0 0 PRR1 • Bit 7 - PRUSB: Power Reduction USB Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re initialized to ensure proper operation. • Bit 6..4 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 3 - PRTiM3: Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/CounterS is enabled, operation will continue like before the shutdown. • Bit 2..1 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 0 - PRUSART1 : Power Reduction USART1 Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re-initialized to ensure proper operation. 8.8 Minimizing power consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 8.8.1 Analog to digital converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis- abled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “ADC - Analog to Digital Converter” on page 307 for details on ADC operation. 8.8.2 Analog comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 304 for details on how to configure the Analog Comparator. 7593L-AVR-09/12 55 8.8.3 Brown-out detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this wiil contribute sig- nificantly to the total current consumption. Refer to “Brown-out detection” on page 60 for details on how to configure the Brown-out Detector. 8.8.4 Internal voltage reference The internal voltage reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal volt- age reference” on page 62 for details on the start-up time. 8.8.5 Watchdog timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to “Interrupts” on page 68 for details on how to configure the Watchdog Timer. 8.8.6 Port pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkyo) and the ADC clock (clk^Dc) stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it wiil then be enabled. Refer to the section “Digital input enable and sleep modes” on page 75 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to Vqq/ 2, the input buffer wiil use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to Vqq/ 2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDRO). Refer to “DIDR1 - Digital Input Disable Register 1” on page 306 and “DIDRO - Digital Input Disable Register 0” on page 326 for details. 8.8.7 On-chip debug system If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to disable the OCD system: • Disable the OCDEN Fuse • Disable the JTAGEN Fuse • Write one to the JTD bit in MCUCR 56 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 9. System control and reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP - Absolute Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 9-1 on page 58 shows the reset logic. Table 9-1 on page 58 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in “Clock sources” on page 41 . 9.2 Reset sources The Atmel AT90USB64/128 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (Vpoj) • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled • Brown-out Reset. The MCU is reset when the supply voltage Vqq is below the Brown-out Reset threshold (Vgoi) the Brown-out Detector is enabled • JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to Section “IEEE 1 149.1 (JTAG) boundary- scan” on page 333 for details 7593L-AVR-09/12 57 Figure 9-1 . Reset logic. DATA BUS LU CO LU d: Table 9-1 . Reset characteristics. Symbol Parameter Condition Min. Typ. Max. Units VpOT Power-on reset threshold voltage (rising) 1.4 2.3 V Power-on reset threshold voltage (falling) 1.3 2.3 VpOR Vqq start voltage to ensure internal power- on reset signal -0.1 0.1 ^CCRR Vqq rise rate to ensure internal power_on reset signal 0.3 V/ms ^RST RESET pin threshold voltage 0.2 ^cc 0.85 ^cc V fRST Minimum pulse width on RESET Pin 5V, 25°C 400 ns Notes: 1 . The POR will not work unless the supply voltage has been below VpQj (falling). 9.3 Power-on reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Table 9-1. The POR is activated whenever Vqq is below the detection level. The POR circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is properly reset from Power-on if Vcc started from VpoR with a rise rate upper than Vqqrr. Reaching the Power-on Reset threshold 58 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 voltage invokes the delay counter, which determines how long the device is kept in RESET after Vqq rise. The RESET signal is activated again, without any delay, when Vcc decreases below the detection level. Figure 9-2. MCU start-up, RESET tied to Vcc- INTERNAL RESET Figure 9-3. Vcc MCU start-up, RESET extended externally. RESET TIMEOUT INTERNAL RESET *TOUT Note: If VpoR or Vqqrr parameter range can not be followed, an external reset is required. 9.4 External reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 9-1 on page 58) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - V^gj - on its positive edge, the delay counter starts the MCU after the Time-out period - tjouT" has expired. 7593L-AVR-09/12 59 Figure 9-4. External reset during operation. Vcc RESET TIMEOUT INTERNAL RESET 9.5 Brown-out detection Atmel AT90USB64/128 has an on-chip Brown-out Detection (BOD) circuit for monitoring the Vqq level during operation by comparing it to a fixed trigger level. The trigger ievel for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as Vbot+ = ^bot + Vhyst/ 2 and Vbot- - Vbot ■ Vhyst/2- Table 9-2. BODLEVEL fuse coding. BODLEVEL 2..0 Fuses Min. Vbot Typ. Vbot Max. Vbot Units 111 BOD disabled 110 Reserved 101 100 oil 2.4 2.6 2.8 V 010 3.2 3.4 3.6 001 3.3 3.5 3.7 000 4.1 4.3 4.5 Table 9-3. Brown-out characteristics. Symboi Parameter Min. Typ. Max. Units Vhyst Brown-out detector hysteresis 50 mV *600 Min. pulse width on brown-out reset ns Ibod Brown-out detector consumption 25 pA When the BOD is enabied, and Vqc decreases to a value below the trigger level (Vbqt- in Figure 9-5 on page 61), the Brown-out Reset is immediately activated. When Vqq increases above the trigger level (Vbot+ in Figure 9-5 on page 61), the delay counter starts the MCU after the Time- out period tjouT expired. The BOD circuit wiil only detect a drop in Vqq if the voltage stays below the trigger level for lon- ger than tgoD given in Table 9-1 on page 58. 60 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 9-5. Brown-out reset during operation. RESET TIMEOUT INTERNAL RESET Vbot+ ‘tout :f 9.6 Watchdog reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tjouT- Refer to page 63 for details on operation of the Watchdog Timer. Figure 9-6. Watchdog reset during operation. ^cc RESET ^1 WDT TIME-OUT 1 CK C cle RESET ! 1 1 1 1 MOUl ' TIME-OUT 1 INTERNAL RESET 9.6.1 MCUSR - MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/write Initial value 7 6 5 4 3 2 1 0 1 - - - JTRF WDRF BORF EXTRF PORF 1 R R R R/W R/W R/W R/W R/W 0 0 0 See bit description MCUSR • Bit 4 - JTRF: JTAG Reset Fiag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Fiag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. ^iniEL 7593L-AVR-09/12 61 • Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 9.7 Internal voltage reference Atmel AT90USB64/128 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.7.1 Voltage reference enable signals and start-up time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 9-4. To save power, the reference is not always turned on. The reference is on during the following situations: 1 . When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 9-4. Internal voltage reference characteristics. Symbol Parameter Condition Min. Typ. Max. Units ^BG Bandgap reference voltage 1.0 1.1 1.2 V *BG Bandgap reference start-up time 40 70 ps ^BG Bandgap reference current consumption 10 pA 62 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 9.8 Watchdog timer The Atmel AT90USB64/128 has an enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate on-chip oscillator • Three operating modes - Interrupt - System reset - Interrupt and system reset • Selectable time-out period from 16ms to 8s • Possible hardware fuse watchdog always on (WDTON) for fail-safe mode Figure 9-7. Watchdog timer. The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up In case of runaway code. The third mode. Interrupt and System Reset mode, combines the other two modes by first giving an inter- rupt and then switch to System Reset mode. This mode will for Instance allow a safe shutdown by saving critical parameters before a system reset. The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys- tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera- tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: ^iniEL « 7593L-AVR-09/12 63 1 . In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. Assembly code example WDT_of f : ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in rl6, MCUSR and! rl6, ~(0< nop y ^ inr17, PINx ^ SYNC LATCH PiNxn 0x00 X OxFF 1 r The foiiowing code exampie shows how to set port B pins 0 and 1 high, 2 and 3 iow, and define the port pins from 4 to 7 as input with puii-ups assigned to port pins 6 and 7. The resuiting pin vaiues are read back again, but as previousiy discussed, a nop instruction is inciuded to be abie to read back the vaiue recentiy assigned to some of the pins. AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Assembly code example ; Define pull-ups and set outputs high ; Define directions for port pins Idi rl6, (1< emS — ► DIxn PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn; Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn; Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn; Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP; SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE PUD; PULLUP DISABLE M WDx: WRITE DDRx 1 RDx; READ DDRx ’ RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk,/o; I/O CLOCK DIxn: DIGITAL INPUT PIN n ON PORTx AlOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1 . WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk|/o, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. 76 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Fig- ure 11-5 on page 76 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2. Generic description of overriding signals for alternate functions. Signal name Full name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = ObOIO. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. PVOV Port Value Override Value If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. PTOE Port Toggle Override Enable If PTOE is set, the PORTxn Register bit is inverted. DIEOE Digital Input Enable Override Enable If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). DIEOV Digital Input Enable Override Value If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). Dl Digital Input This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. AlO Analog Input/Output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 7593L-AVR-09/12 77 1 1 .3.1 MCUCR - MCU Control Register Bit 7 6 5 4 3 2 1 0 1 JTD - - PUD - - IVSEL IVCE ] MCUCR Read/write R/W R R R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 • Bit 4 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = ObOl). See “Con- figuring the pin” on page 72 for more details about this feature. 1 1 .3.2 Alternate functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 11-3. Port A pins alternate functions. Port pin Alternate function PA7 AD7 (External memory interface address and data bit 7) PA6 AD6 (External memory interface address and data bit 6) PA5 ADS (External memory interface address and data bit 5) PA4 AD4 (External memory interface address and data bit 4) PA3 AD3 (External memory interface address and data bit 3) PA2 AD2 (External memory interface address and data bit 2) PA1 ADI (External memory interface address and data bit 1) PAO ADO (External memory interface address and data bit 0) Table 11-4 and Table 1 1-5 on page 79 relates the alternate functions of Port A to the overriding signals shown in Figure 11-5 on page 76. Table 11-4. Overriding signals for alternate functions in PA7..PA4. Signal name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4 PUOE SRE SRE SRE SRE PUOV ~(WR I ADA <^)) • PORTA7 • PUD ~(WR I ADA) • PORTA6 • PUD ~(WR I ADA) • PORTA5 • PUD ~(WR I ADA) • PORTA4 • PUD DDOE SRE SRE SRE SRE DDOV WR I ADA WR I ADA WR I ADA WR I ADA PVOE SRE SRE SRE SRE PVOV A7 • ADA I D7 OUTPUT • WR A6 • ADA I D6 OUTPUT • WR AS • ADA I DS OUTPUT* WR A4 • ADA I D4 OUTPUT • WR DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl D7 INPUT D6 INPUT DS INPUT D4 INPUT AlO - - - - 78 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Note: 1 . ADA is short for ADdress Active and represents the time when address is output. See “Exter- nal memory interface” on page 31 for details. Table 11-5. Overriding signals for alternate functions in PA3..PA0. Signal name PA3/AD3 PA2/AD2 PA1/AD1 PAO/ADO PUOE SRE SRE SRE SRE PUOV ~(WR 1 ADA) • PORTA3 • PUD ~(WR I ADA) • PORTA2 • PUD ~(WR 1 ADA) • PORTA1 • PUD ~(WR I ADA) • PORTAO • PUD DDOE SRE SRE SRE SRE DDOV WR 1 ADA WR I ADA WR I ADA WR 1 ADA PVOE SRE SRE SRE SRE PVOV A3 • ADA 1 D3 OUTPUT • WR A2* ADA 1 D2 OUTPUT • WR A1 • ADA 1 Dl OUTPUT* WR AO • ADA 1 DO OUTPUT* WR DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl D3 INPUT D2 INPUT Dl INPUT DO INPUT AlO - - - - 1 1 .3.3 Alternate functions of Port B The Port B pins with alternate functions are shown in Table 11-6. Table 11-6. Port B pins alternate functions. Port pin Alternate functions PB7 OCOA/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/CounterO, Output Compare and PWM Output C for Timer/Counterl or Pin Change Interrupt 7) PB6 OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counterl or Pin Change Interrupt 6) PBS OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counterl or Pin Change Interrupt 5) PB4 OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt 4) PB3 PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave Output or Pin Change Interrupt 3) PB2 PDI/MOSI/PCINT2 (Programming Data Input orSPI Bus Master Output/Slave Input or Pin Change Interrupt 2) PB1 SCK/PCINT 1 (SPI Bus Serial Clock or Pin Change Interrupt 1 ) PBO SS/PCINTO (SPI Slave Select input or Pin Change Interrupt 0) The alternate pin configuration is as follows: • OCOA/OC1C/PCINT7, bit? OCOA, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/CounterO Output Compare. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OCOA pin is also the output pin for the PWM mode timer function. 7593L-AVR-09/12 79 0C1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Countert Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1 C pin is also the output pin for the PWM mode timer function. PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT6, bite OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Countert Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1 B pin is also the output pin for the PWM mode timer function. PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source. • OC1A/PCINT5, bits OC1 A, Output Compare Match A output: The PBS pin can serve as an external output for the Timer/Countert Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1 A pin is also the output pin for the PWM mode timer function. PCINT5, Pin Change Interrupt source 5: The PBS pin can serve as an external interrupt source. • OC2A/PCiNT4, bit 4 OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source. • PDO/MiSO/PCiNT3 - Port B, bit 3 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the Atmel AT90USB64/128. MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source. • PDI/MOSI/PCINT2 - Port B, bit 2 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the AT90USB64/1 28. MOSI: SPI Master Data output. Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source. • SCK/PCINT1 - Port B, bit 1 SCK: Master Clock output. Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPIO is enabled as a master, the data direction of this pin is controlled by DDB1 . When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. 80 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source. • ^/PCINTO - Port B, bit 0 SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDBO. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDBO. When the pin is forced to be an input, the pull-up can still be controlled by the PORTBO bit. Table 11-7 and Table 11-8 relate the alternate functions of Port B to the overriding signals shown in Figure 11-5 on page 76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. PCINTO, Pin Change Interrupt source 0: The PBO pin can serve as an external interrupt source.. Table 11-7. Overriding signals for alternate functions in PB7..PB4. Signal name PB7/PCINT7/OCOA/ OC1C PB6/PCINT6/OC1 B PB5/PCINT5/OC1A PB4/PCINT4/OC2A PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OCO/OC1C ENABLE OC1B ENABLE OC1A ENABLE OC2A ENABLE PVOV OCO/OC1C OC1B OC1A OC2A DIEOE PCINT7* PCIEO PCINT6* PCIEO POINTS • PCIEO PCINT4* PCIEO DIEOV 1 1 1 1 Dl PCINT7 INPUT PCINT6 INPUT POINTS INPUT PCINT4 INPUT AlO - - - - Table 11-8. Overriding signals for alternate functions in PBS. .PBO. Signal name PB3/PD0/PCINT3/ MISO PB2/PDI/PCINT2/ MOSI PB1/PCINT1/ SCK PBO/PCINTO/ SS PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTBO • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0 0 0 0 PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0 PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0 DIEOE POINTS* PCIEO PCINT2* PCIEO PCINT1 • PCIEO PCINTO* PCIEO DIEOV 1 1 1 1 Dl SPI MSTR INPUT POINTS INPUT SPI SLAVE INPUT PCINT2 INPUT SCK INPUT PCINT1 INPUT SPI SS PCINTO INPUT AlO - - - - 7593L-AVR-09/12 81 1 1 .3.4 Alternate functions of Port C The Port C alternate function is as follows: Table 11-9. Port C pins alternate functions. Port pin Alternate function PC7 A1 5/IC.3/CLKO(External Memory interface address bit 1 5 or Input Capture Timer 3 or CLKO (Divided System Clock) PC6 A14/OC.3A(External Memory interface address bit 14 or Output Compare and PWM output A for Timer/Counter3) PC5 A13/OC.3B(External Memory interface address bit 13 or Output Compare and PWM output B for Timer/Counter3) PC4 A12/OC.3C(External Memory interface address bit 12 or Output Compare and PWM output C for Timer/Counter3) PC3 A1 1Ar.3(External Memory interface address bit 11orTimer/Counter3 Clok Input) PC2 A10(External Memory interface address bit 10) PCI A9(External Memory interface address bit 9) PCO A8(External Memory interface address bit 8) Table 11-10 and Table 11-11 on page 83 relate the alternate functions of Port C to the overriding signals shown in Figure 1 1-5 on page 76. Table 11-10. Overriding signals for alternate functions in PC7..PC4. Signal name PC7/A15/IC.3/CLKO PC6/A14/OC.3A PC5/A13/OC.3B PC4/A12/OC.3C PUOE SRE*(XMM<1) SRE* (XMM<2)|OC3A enable SRE* (XMM<3)|OC3B enable SRE* (XMM<4)|OC3C enable PUOV 0 0 0 0 DDOE SRE*(XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE * (XMM<4) DDOV 1 1 1 1 PVOE SRE*(XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE * (XMM<4) PVOV A15 if (SRE.XMM<2) then A14 else OC3A if (SRE.XMM<2) then A13 else OC3B if (SRE.XMM<2) then A12 else OC3C DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl ICP3 input - - - AlO - - - - 82 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 11-11. Overriding signals for alternate functions in PC3..PC0. Signal name PC3/A11/T.3 PC2/A10 PC1/A9 PC0/A8 PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV 0 0 0 0 DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMI\/I<7) SRE • (XMM<7) DDOV 1 1 1 1 PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PVOV All A10 A9 A8 DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl T3 input - - - AlO - - - - 1 1 .3.5 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 11-12. Table 11-12. Port D pins alternate functions. Port pin Alternate function PD7 TO (Timer/CounterO Clock Input) PD6 T1 (Timer/Counterl Clock Input) PD5 XCK1 (USART1 External Clock Input/Output) PD4 ICP1 (Timer/Counterl Input Capture Trigger) PD3 InTs/TXDI (External Interrupt3 Input or USART1 Transmit Pin) PD2 INT2/RXD1 (External Interrupt2 Input or USART1 Receive Pin) PD1 INT1/SDA/OC2B (External Interrupti Input orTWI Serial DAta or Output Compare for Timer/Counter2) PDO INTO/SCLVOCOB (External InterruptO Input orTWI Serial Clock or Output Compare for Timer/CounterO) The alternate pin configuration is as follows: • TO - Port D, bit 7 TO, Timer/CounterO counter source. • T1 - Port D, bit 6 T1, Timer/Counterl counter source. • XCK1 - Port D, bit 5 XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates In Synchronous mode. ^iniEL 7593L-AVR-09/12 83 • ICP1 - Port D, bit 4 ICP1 - Input Capture Pin 1 : The PD4 pin can act as an input capture pin for Timer/Countert . • iNT3/TXD1 - Port D, bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1 , Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • iNT2/RXD1 - Port D, bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit. • INT1/SDA/OC2B - Port D, bit 1 INTI, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. • INTO/SCI_/OCOB - Port D, bit 0 INTO, External Interrupt source 0. The PDO pin can serve as an external interrupt source to the MCU. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2- wire Serial Interface, pin PDO is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 1 1-13 on page 85 and Table 1 1-14 on page 85 relates the alternate functions of Port D to the overriding signals shown in Figure 1 1-5 on page 76. 84 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 11-13. Overriding signals for alternate functions PD7..PD4. Signal name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl TO INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AlO - - - - Table 11-14. Overriding signals for alternate functions in PD3..PD0 PD1/INT1/SDA/OC2 PDO/INTO/SCL/OCO Signal name PD3/INT3/TXD1 PD2/INT2/RXD1 B B PUOE TXEN1 RXEN1 TWEN TWEN PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTDO • PUD DDOE TXEN1 RXEN1 TWEN TWEN DDOV 1 0 SDA_OUT SCL_OUT PVOE TXEN1 0 TWEN I OC2B TWEN 1 OCOB ENABLE ENABLE PVOV TXD1 0 OC2B OCOB DIEOE INT3 ENABLE INT2 ENABLE INTI ENABLE INTO ENABLE DIEOV 1 1 1 1 Dl INT3 INPUT INT2 INPUT/RXD1 INTI INPUT INTO INPUT AlO - - SDA INPUT SOL INPUT Note: 1 . When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PDO and PD1. This is not shown in this table. In addition, spike filters are connected between the AlO outputs shown In the port figure and the digital logic of the TWI module. ^iniEL 7593L-AVR-09/12 85 11.3.6 Alternate functions of Port E The Port E pins with alternate functions are shown in Table 11-15. Table 11-15. Port E pins alternate functions. Port pin Alternate function PE7 INT7/AIN.1/UVCON (External Interrupt 7 Input, Analog Comparator Positive Input or VBUS Control) PE6 INT6/AIN.0 (External Interrupt 6 Input or Analog Comparator Positive Input) PE5 INT5/TOSC2 (External Interrupt 5 Input or RTC Oscillator Timer/Counter2)) PE4 INT4/TOSC2 (External Interrupt4 Input or RTC Oscillator Timer/Counter2) PE3 UID PE2 ALE/HWB (Address latch to extenal memory or Hardware bootloader activation) PEI RD (Read strobe to external memory) PEO WR (Write strobe to external memory) • INT7/AIN.1/UVCON - Port E, bit 7 INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. AIN1 - Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. UVCON - When using USB host mode, this pin allows to control an external VBUS generator (active high). • INT6/AIN.0 - Port E, bite INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. AINO - Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. • INT5/TOSC2 - Port E, bit 5 INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source. TOSC2, Timer/Counter2 Oscillator pinl. When the AS2 bit in ASSR is set to enable asynchro- nous clocking of Timer/Counter2, pin PE5 is disconnected from the port, and becomes the ouput of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin can not be used as an I/O pin. • iNT4/TOSC1 - Port E, bit 4 INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source. TOSC1, Timer/Counter2 Oscillator pin2. When the AS2 bit in ASSR is set to enable asynchro- nous clocking of Timer/Counter2, pin PE4 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin can not be used as an I/O pin. • UiD - Port E, bit 3 ID pin of the USB bus. 86 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 • ALE/HWB - Port E, bit 2 ALE is the external data memory Address latch enable. HWB allows to execute the boot loader section after reset when tied to ground during external reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable. • RD - Port E, bit 1 RD is the external data memory read control enable. • WR - Port E, bit 0 WR is the external data memory write control enable. Table 11-16. Overriding signals for alternate functions PE7..PE4. Signal name PE7/INT7/AIN.1/ UVCON PE6/INT6/AIN.0 PES/INTSTTOSCI PE4/INT4/TOSC2 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE UVCONE 0 0 0 DDOV UVCONE 0 0 0 PVOE UVCONE 0 0 0 PVOV UVCON 0 0 0 DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DIEOV 1 1 1 1 Dl INT7 INPUT INT6 INPUT INT5 INPUT INT4 INPUT AlO AIN1 INPUT AINO INPUT - - Table 11-17. Overriding signals for alternate functions in PE3..PE0. Signal name PE3/UID PE2/ALE/HWB PE1/RD PEO/WR PUOE UIDE 0 SRE SRE PUOV 1 0 0 0 DDOE UIDE SRE SRE SRE DDOV 0 1 1 0 PVOE 0 SRE SRE SRE PVOV 0 ALE RD WR DIEOE UIDE 0 0 0 DIEOV 1 0 0 1 Dl UID HWB - - PEO 0 0 0 0 AlO - - - - ^iniEL 7593L-AVR-09/12 87 1 1 .3.7 Alternate functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 11-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a con- version is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 11-18. Port F pins alternate functions. Port pin Alternate function PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) PF3 ADC3 (ADC input channel 3) PF2 ADC2 (ADC input channel 2) PF1 ADC1 (ADC input channel 1) PFO ADCO (ADC input channel 0) • TDI, ADC7 - Port F, bit 7 ADC7, Analog to Digital Converter, Channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg- ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TDO, ADC6 - Port F, bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TDO pin is tri-stated unless TAP states that shift out data are entered. • TMS, ADCS - Port F, bit 5 ADCS, Analog to Digital Converter, Channel 5. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 - Port F, bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 - ADCO - Port F, bit 3..0 Analog to Digital Converter, Channel 3..0. 88 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 11-19. Overriding signals for alternate functions in PF7..PF4. Signal name PF7/ADC7/TDI PFS/ADCe/TDO PFS/ADCSA'MS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFTJR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 Dl - - - - AlO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 11-20. Overriding signals for alternate functions in PF3..PF0. Signal name PF3/ADC3 PF2/ADC2 PF1/ADC1 PFO/ADCO PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 Dl - - - - AlO ADCS INPUT ADC2 INPUT ADC1 INPUT ADCO INPUT 11 .4 Register description for l/O-ports 11.4.1 PORTA - Port A Data Register Bit 7 6 5 4 3 2 1 0 1 P0RTA7 P0RTA6 PORTA5 P0RTA4 PORTA3 P0RTA2 P0RTA1 PORTAO Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PORTA ^iniEL 7593L-AVR-09/12 89 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 11.4.10 DDRA - Port A Data Direction Register Bit 7 6 5 4 3 2 1 0 I^^DDAT^^ DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDAO I DDRA Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PiNA - Port A input Pins Address Bit 7 6 5 4 3 2 1 0 1 PINA7 PINA6 PINAS PINA4 PINAS PINA2 PINA1 PINAO I PINA Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value N/A N/A N/A N/A N/A N/A N/A N/A PORTS - Port B Data Register Bit 7 6 5 4 3 2 1 0 1 PORTB7~ PORTB6 PORTB5 PORTB4 PORTB3 P0RTB2 PORTB1 PORTBO I PORTB Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRB - Port B Data Direction Register Bit 7 6 5 4 3 2 1 0 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO I DDRB Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PiNB - Port B input Pins Address Bit 7 6 5 4 3 2 1 0 1 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINBO I PINB Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value N/A N/A N/A N/A N/A N/A N/A N/A PORTC - Port C Data Register Bit 7 6 5 4 3 2 1 0 I^^PORTC^ PORTC6 PORTC5 PORTC4 PORTC3 P0RTC2 PORTC1 PORTCO I PORTC Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRC - Port C Data Direction Register Bit 7 6 5 4 3 2 1 0 DDC6 DDC5 DDC4 DDC3 □ DC2 DDC1 DDCO I DDRC Read/write R/W R/W RAW R/W R/W R/W R/W RAW Initial value 0 0 0 0 0 0 0 0 PiNC - Port C input Pins Address Bit 7 6 5 4 3 2 1 0 1 PINC7 PINC6 PINCS PINC4 PINCS PINC2 PINC1 PINCO I PINC Read/write R/W R/W RAW R/W R/W R/W R/W RAW Initial value N/A N/A N/A N/A N/A N/A N/A N/A PORTD - Port D Data Register Bit 7 6 5 4 3 2 1 0 1 PORTD7~ PORTD6 PORTD5 PORTD4 PORTD3 P0RTD2 PORTD1 PORTDO I PORTD Read/write R/W R/W RAW R/W R/W R/W R/W RAW Initial value 0 0 0 0 0 0 0 0 90 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 11.4.11 11.4.12 11.4.13 11.4.14 11.4.15 11.4.16 11.4.17 11.4.18 DDRD - Port D Data Direction Register Bit 7 6 5 4 3 2 1 0 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO 1 DDRD Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PiND - Port D input Pins Address Bit 7 6 5 4 3 2 1 0 1 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO 1 PIND Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value N/A N/A N/A N/A N/A N/A N/A N/A PORTE - Port E Data Register Bit 7 6 5 4 3 2 1 0 1 PORTE7 ~ PORTE6 PORTE5 PORTE4 PORTE3 P0RTE2 PORTE1 PORTED 1 PORTE Read/write R/W R/W RAW R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRE - Port E Data Direction Register Bit 7 6 5 4 3 2 1 0 DDE6 DDES DDE4 DDE3 DDE2 DDE1 DDEO 1 DDRE Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PiNE - Port E input Pins Address Bit 7 6 5 4 3 2 1 0 1 PINE7 PINE6 PINES PINE4 PINE3 PINE2 PINE1 PINED 1 PINE Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value N/A N/A N/A N/A N/A N/A N/A N/A PORTF - Port F Data Register Bit 7 6 5 4 3 2 1 0 1 PORTF7 ~ PORTF6 PORTFS PORTF4 PORTF3 PORTF2 PORTF1 PORTED 1 PORTF Read/write R/W R/W RAW R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DDRF - Port F Data Direction Register Bit 7 6 5 4 3 2 1 0 DDF6 DDFS DDF4 DDF3 DDF2 DDF1 DDFD 1 DDRF Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PiNF - Port F input Pins Address Bit 7 6 5 4 3 2 1 0 1 PINF7 PINF6 PINFS PINF4 PINF3 PINF2 PINF1 PINFD 1 PINF Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value N/A N/A N/A N/A N/A N/A N/A N/A ^iniEL 7593L-AVR-09/12 91 12. External interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT7..0 pins are configured as oufputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCIO will trigger if any enabied PCINT7:0 pin toggles. PCMSKO Regis- ter control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes ofher than Idle mode. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupfs on INT7:4 requires fhe presence of an I/O clock, described in “System ciock and clock options” on page 40. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of fhe Sfart-up Time, the MCU will still wake up, but no inter- rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System clock and clock options” on page 40. 12.0.1 EICRA - External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/write Initial value 7 6 5 4 3 2 1 0 1 ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISCOO I R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 EICRA • Bits 7..0 - ISC31 , ISC30 - ISCOO, ISCOO: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG l-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 12-1. Edges on INT3..INT0 are registered asynchro- nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Tabie 12-2 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupf is selecfed, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level friggered interrupt will generate an inter- rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt fiag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before fhe interrupt is re-enabled. 92 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 1 2-1 . Interrupt sense control ISCn1 ISCnO Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: 1. n = 3, 2, 1or0. When changing the ISCn1/ISCnO bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. Table 12-2. Asynchronous external interrupt characteristics. Symbol Parameter Condition Min. Typ. Max. Units t|NT Minimum pulse width for asynchronous external interrupt 50 ns 12.0.2 EICRB - External Interrupt Control Register B Bit 7 6 5 4 3 2 1 0 1 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 • Bits 7..0 - ISC71 , ISC70 - ISC41 , ISC40: External Interrupt 7-4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG l-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 12-3. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter- rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the comple- tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 12-3. Interrupt sense control ISCn1 ISCnO Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request. 1 0 The falling edge between two samples of INTn generates an interrupt request. 1 1 The rising edge between two samples of INTn generates an interrupt request. Note: 1. n = 7, 6, 5or4. When changing the ISCnI/ISCnO bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. 12.0.3 EIMSK - External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 1 INT7 INT6 INT5 INT4 INT3 INT2 INT1 UNTO I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EIMSK 7593L-AVR-09/12 93 12.0.4 12.0.5 12.0.6 • Bits 7..0 - INT7 - INTO: External Interrupt Request 7-0 Enable When an INT7 - INTO bit is written to one and the l-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB - defines whether the external inter- rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. EIFR - External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 1 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 lINTFO 1 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 • Bits 7..0 - INTF7 - INTFO: External Interrupt Flags 7-0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the l-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital input enable and sleep modes” on page 75 for more information. PCiCR - Pin Change interrupt Controi Register Bit 7 6 5 4 3 2 1 0 1 - - - - - PCIEO 1 PCICR Read/write R R R R R R R R/W Initial value 0 0 0 0 0 0 0 0 • Bit 0 - PCIEO: Pin Change interrupt Enabie 0 When the PCIEO bit is set (one) and the l-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCIO Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSKO Register. PCiFR - Pin Change interrupt Fiag Register Bit 7 6 5 4 3 2 1 0 _____ ^CIFO^J PCIFR Read/write R R R R R R R R/W Initial value 00000000 • Bit 0 - PCiFO: Pin Change interrupt Fiag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIFO becomes set (one). If the l-bit in SREG and the PCIEO bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 94 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 12.0.7 PCMSKO - Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 1 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PCMSKO • Bit 7..0 - PCiNT7..0: Pin Change Enabie Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIEO bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ^iniEL 7593L-AVR-09/12 95 13. Timer/CounterO, Timer/Counterl, and Timer/CounterS prescalers Timer/CounterO, 1 , and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1 or 3. 13.1 Internal clock source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fcLKj/o)- Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fcLKj/o/8, fcLK_i/o/64, fcLK_i/o/256, or fcLK_i/c/1 024. 13.2 Prescaler reset The prescaler is free running, that is, operates independently of the Clock Select logic of the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artefacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu- tion. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 13.3 External clock source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkj^). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro- nized (sampled) signal Is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clk|/o). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkjn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 13-1. Tn/TO pin sampling. The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse Is generated. 96 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (fExtcik < given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f^n^ i/o/2.5. An external clock source can not be prescaled. Figure 13-2. Prescaler for synchronous Timer/Counters 13.4 GTCCR - General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 1 TSM - - - - - PSRASY PSRSYNC 1 Read/write R/W R R R R R R/W RAW Initial value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond- ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 - PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/CounterO and Timer/Counterf and Timer/CounterS prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/CounterO, Timer/Counterf and Timer/CounterS share the same prescaler and a reset of this prescaler will affect all timers. ^rniEL « 7593L-AVR-09/12 97 14. 8-bit Timer/CounterO with PWM Timer/CounterO is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • Two independent output compare units • Doubie buffered output compare registers • Ciear timer on compare match (auto reioad) • Giitch free, phase correct puise width moduiator (PWM) • Variabie PWM period • Frequency generator • Three independent interrupt sources (TOVO, OCFOA, and OCFOB) 14.1 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to “Pinout Atmel AT90USB64/128-TQFP.” on page 3. CPU accessi- ble I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter register description” on page 108. Figure 14-1. 8-bit Timer/Counter block diagram. CO Z) CD I Q 14.1.1 Registers The Timer/Counter (TCNTO) and Output Compare Registers (OCROA and OCROB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRO). All interrupts are individually masked with the Timer Inter- rupt Mask Register (TIMSKO). TIFRO and TIMSKO are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the TO pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkjg). 98 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 The double buffered Output Compare Registers (OCROA and OCROB) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output on the Output Compare pins (OCOA and OCOB). See “Output compare unit” on page 100. for details. The Compare Match event will also set the Compare Flag (OCFOA or OCFOB) which can be used to generate an Output Compare interrupt request. 14.1.2 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, In this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNTO for accessing Timer/CounterO counter value and so on. The definitions in the table below are also used extensively throughout the document. BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes OxFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value OxFF (MAX) or the value stored in the OCROA Register. The assignment is dependent on the mode of operation. 14.2 Timer/Counter clock sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCROB). For details on clock sources and pres- caler, see “Timer/CounterO, Timer/Counterl, and Timer/CounterS prescalers” on page 96. 14.3 Counter unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter unit block diagram. ^iniEL « 7593L-AVR-09/12 99 Signal description (internal signals): top bottom count direction ciear clky. ‘Tn Increment or decrement TCNTO by 1 . Select between increment and decrement. Clear TCNTO (set all bits to zero). Timer/Counter clock, referred to as clkjo in the following. Signalize that TCNTO has reached maximum value. Signalize that TCNTO has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkjo). clkjo can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNTO value can be accessed by the CPU, regardless of whether clkjg is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGMOO bits located in the Timer/Counter Control Register (TCCROA) and the WGM02 bit located in the Timer/Counter Control Register B (TCCROB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCOA and OCOB. For more details about advanced counting sequences and waveform generation, see “Modes of operation” on page 103. The Timer/Counter Overflow Flag (TOVO) is set according to the mode of operation selected by the WGM02:0 bits. TOVO can be used for generating a CPU interrupt. 14.4 Output compare unit The 8-bit comparator continuously compares TCNTO with the Output Compare Registers (OCROA and OCROB). Whenever TCNTO equals OCROA or OCROB, the comparator signals a match. A match will set the Output Compare Flag (OCFOA or OCFOB) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe- cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The maximum and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of operation” on page 103). Figure 14-3 on page 101 shows a block diagram of the Output Compare unit. 100 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 14-3. Output Compare Unit, block diagram. WGMn1:0 COMnX1:0 The OCROx Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled. The double buffering synchronizes the update of the OCROx Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCROx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCROx Buffer Register, and if double buffering is dis- abled the CPU will access the OCROx directly. 14.4.1 Force output compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCOx) bit. Forcing Compare Match will not set the OCFOx Flag or reload/clear the timer, but the OCOx pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OCOx pin is set, cleared or toggled). 14.4.2 Compare match blocking by TCNTO write All CPU write operations to the TCNTO Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCROx to be initial- ized to the same value as TCNTO without triggering an interrupt when the Timer/Counter clock is enabled. 14.4.3 Using the output compare unit Since writing TCNTO in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNTO when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNTO equals the OCROx value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNTO value equal to BOTTOM when the counter is down-counting. ^iniEL 7593L-AVR-09/12 101 The setup of the OCOx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCOx value is to use the Force Output Com- pare (FOCOx) strobe bits in Normal mode. The OCOx Registers keep their values even when changing between Waveform Generation modes. Be aware that the COMOxI :0 bits are not double buffered together with the compare value. Changing the COMOxI :0 bits wiil take effect immediately. 14.5 Compare Match Output Unit The Compare Output mode (COMOxI :0) bits have two functions. The Waveform Generator uses the COMOxI :0 bits for defining the Output Compare (OCOx) state at the next Compare Match. Also, the COMOxI :0 bits control the OCOx pin output source. Figure 14-4 shows a simplified schematic of the logic affected by the COMOxI :0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMOxI :0 bits are shown. When referring to the OCOx state, the reference is for the internal OCOx Register, not the OCOx pin. If a system reset occur, the OCOx Register is reset to “0”. Figure 14-4. Compare Match Output Unit, schematic. The general I/O port function is overridden by the Output Compare (OCOx) from the Waveform Generator if either of the COMOxI :0 bits are set. However, the OCOx pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCOx pin (DDR_OCOx) must be set as output before the OCOx value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OCOx state before the out- put is enabled. Note that some COMOxI :0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter register description” on page 108. 14.5.1 Compare output mode and waveform generation The Waveform Generator uses the COMOxI :0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COMOxI :0 = 0 tells the Waveform Generator that no action on the OCOx Register is to be performed on the next Compare Match. For compare output actions in 102 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 the non-PWM modes refer to Table 14-1 on page 109. For fast PWM mode, refer to Table 14-2 on page 109, and for phase correct PWM refer to Table 14-3 on page 109. A change of the COMOxI :0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCOx strobe bits. 14.6 Modes of operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Out- put mode (COMOxI :0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMOxI :0 bits control whether the PWM out- put generated should be Inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMOxI :0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 102.). For detailed timing information see “Timer/Counter timing diagrams” on page 107. 14.6.1 Normal mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = OxFF) and then restarts from the bot- tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOVO) will be set in the same timer clock cycle as the TCNTO becomes zero. The TOVO Flag In this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVO Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 14.6.2 Clear Timer on Compare Match (CTC) mode In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCROA Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTO) matches the OCROA. The OCROA defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 14-5 on page 104. The counter value (TCNTO) increases until a Compare Match occurs between TCNTO and OCROA, and then coun- ter (TCNTO) Is cleared. 7593L-AVR-09/12 103 Figure 14-5. CTC mode, timing diagram. An interrupt can be generated each time the counter value reaches the TOP value by using the OCFOA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run- ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCROA is lower than the current value of TCNTO, the counter will miss the Compare Match. The counter will then have to count to its maximum value (OxFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OCOA output can be set to toggle its logical level on each Compare Match by setting the Compare Cutput mode bits to toggle mode (CCM0A1 :0 = 1 ). The CCOA value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of foco = fcik 1/0^2 when CCROA is set to zero (0x00). The waveform frequency is defined by the following equation: r ^ h\k_\IO JoCnx 2■N■{^+OCRnx) The A/ variable represents the prescale factor (1 , 8, 64, 256, or 1024). As for the Normal mode of operation, the TCVO Flag Is set in the same timer clock cycle that the counter counts from MAX to 0x00. 14.6.3 Fast PWM mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre- quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BCTTCM to TCP then restarts from BCT- TCM. TCP Is defined as OxFF when WGM2:0 = 3, and CCROA when WGM2:0 = 7. In non- inverting Compare Cutput mode, the Cutput Compare (CCOx) is cleared on the Compare Match between TCNTO and CCROx, and set at BCTTCM. In Inverting Compare Cutput mode, the out- put is set on Compare Match and cleared at BCTTCM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TCP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 104 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 PWM mode is shown in Figure 14-6. The TCNTO value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTO slopes represent Com- pare Matches between OCROx and TCNTO. Figure 14-6. Fast PWM mode, timing diagram. Period The Timer/Counter Overflow Flag (TOVO) is set each time the counter reaches TOP. If the inter- rupt is enabled, the Interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OCOx pins. Setting the COMOxI :0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMOxI :0 to three: Setting the COMOA1 :0 bits to one allows the OCOA pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OCOB pin (see Table 14-2 on page 109). The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is gener- ated by setting (or clearing) the OCOx Register at the Compare Match between OCROx and TCNTO, and clearing (or setting) the OCOx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f _ /clk_l/0 ^ OCnxPWM ^ _ 256 The A/ variable represents the prescale factor (1 , 8, 64, 256, or 1024). The extreme values for the OCROA Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCROA is set equal to BOTTOM, the output will be a narrow spike for each MAXh- 1 timer clock cycle. Setting the OCROA equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COMOA1 :0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OCOx to toggle its logical level on each Compare Match (COMOxI :0 = 1). The waveform generated will have a maximum frequency of foco = ^cik_i/o/2 when OCROA is set to zero. This 7593L-AVR-09/12 ® 105 feature is similar to the OCOA toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.6.4 Phase correct PWM mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT- TOM. TOP Is defined as OxFF when WGM2:0 = 1, and OCROA when WGM2:0 = 5. In non- inverting Compare Output mode, the Output Compare (OCOx) is cleared on the Compare Match between TCNTO and OCROx while up-counting, and set on the Compare Match while down- counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the sym- metric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter Is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNTO value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-7. The TCNTO value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTO slopes represent Compare Matches between OCROx and TCNTO. Figure 14-7. Phase correct PWM mode, timing diagram. Period ^ 1 2 3 The Timer/Counter Overflow Flag (TOVO) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an Interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OCOx pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COMOxTO to three: Setting the COMOAO bits to 106 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 one allows the OCOA pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OCOB pin (see Table 14-3 on page 109). The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OCOx Register at the Compare Match between OCROx and TCNTO when the counter increments, and setting (or clearing) the OCOx Register at Com- pare Match between OCROx and TCNTO when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: foCnxPCPWM - ■ /clk_l/0 N - 510 The N variable represents the prescale factor (1 , 8, 64, 256, or 1024). The extreme values for the OCROA Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCROA is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 14-7 on page 106 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCROA changes its value from MAX, like in Figure 14-7 on page 106. When the OCROA value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match • The timer starts counting from a value higher than the one in OCROA, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up 14.7 Timer/Counter timing diagrams The Timer/Counter is a synchronous design and the timer clock (clkjg) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 14-8. Timer/Counter timing diagram, no prescaling. clk|/o Clkxn (clk„o/1) TCNTn TOVn ^ MAX - 1 ^ BOTTOM ^ BOTTOM + 1 Figure 14-9 on page 108 shows the same timing data, but with the prescaler enabled. 7593L-AVR-09/12 107 Figure 14-9. Timer/Counter timing diagram, with prescaler (fdkj/o/S)- W Cl^Tn r ('=IK„o/8) 1 r 1 1 1 n TCNTn ^ MAX - 1 MAX ^ BOTTOM ^ BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCFOB in all modes and OCFOA in all modes except CTC mode and PWM mode, where OCROA is TOP. Figure 14-10. Timer/Counter timing diagram, setting of OCFOx, with prescaler (fcikj/o/^)- clk|/o |~|_ cikth n (clk,„/8) I TCNTn n n n OCRnx - 1 OCRnx ^ OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 14-1 1 shows the setting of OCFOA and the clearing of TCNTO in CTC mode and fast PWM mode where OCROA is TOP. Figure 14-11. Timer/Counter timing diagram, clear timer on Compare Match mode, with pres- caler (fcik_i/o/8) ='K''° FL ‘=">8) ; UBRRLn = (unsigned char) baud; /* Enable receiver and transmitter */ UCSRnB = (l«RXENn) | (l«TXENn); /* Set frame format: Sdata, 2stop bit */ UCSRnC = (l«USBSn) | (3«UCSZnO) ; } Note: 1 . See “About code examples” on page 1 0. More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. 19.5 Data transmission - The USART transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- 182 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 den by the USART and given the function as the transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchro- nous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 19.5.1 Sending frames with 5 to 8 data bits A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register, U2Xn bit or by XCKn depending on mode of operation. The following code examples show a simple USART transmit function based on polling of the Data Register Empty {(JDREn) Flag. When using frames with less than eight bits, the most sig- nificant bits written to the UDRn are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16 Assembly code example USART_Transmit : ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Put data (rl6) into buffer, sends the data out UDRn,rl6 ret C code example void USART_Transinit ( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (l«UDREn)) ) /* Put data into buffer, sends the data */ UDRn = data; } Note: 1 . See “About code examples” on page 1 0. The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. 1 9.5.2 Sending frames with 9 data bits If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCS- RnB before the low byte of the character is written to UDRn. The following code examples show 7593L-AVR-09/12 183 a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly code example USART_Transmit : ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from rl7 to TXB8 cbi UCSRnB,TXB8 sbrc rl7 , 0 sbi UCSRnB,TXB8 ; Put LSB data (rl6) into buffer, sends the data out UDRn,rl6 ret C code example void USART_Transmit ( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (l«UDREn))) ) /* Copy 9th bit to TXB8 */ UCSRnB &= ~(1«TXB8); if ( data & 0x0100 ) UCSRnB 1= (1«TXB8); /* Put data into buffer, sends the data */ UDRn = data; } Notes: 1 . These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See “About code examples” on page 1 0. The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. 19.5.3 Transmitter flags and interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to 184 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present In the transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to Its bit location. The TXCn Flag is useful in half-duplex commu- nication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han- dling routine does not have to clear the TXCn Flag, this is done automatically when the Interrupt is executed. 19.5.4 Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMnI = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 1 9.5.5 Disabling the transmitter The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Trans- mit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn pin. 19.6 Data reception - The USART receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer clock. 1 9.6.1 Receiving frames with 5 to 8 data bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, that is, a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant 7593L-AVR-09/12 185 19.6.2 bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly code example USART_Receive : ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in rl6, UDRn ret C code example unsigned char USART_Receive ( void ) { /* Wait for data to be received */ while ( ! (UCSRnA & (l«RXCn) ) ) /* Get and return received data from buffer */ return UDRn; } Note: 1 . See “About code examples” on page 1 0. The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value. Receiving frames with 9 data bits If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCS- RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which ail are stored in the FIFO, will change. The following code exampie shows a simple USART receive function that handles both nine bit characters and the status bits. 186 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Assembly code example USART_Receive : ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in rl8, UCSRnA in rl7, UCSRnB in rl6, UDRn ; If error, return -1 andi rl8, (l<> 1) & 0x01; return ((resh « 8) | resl); } Note: 1 . See “About code examples” on page 1 0. The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 19.6.3 Receive compete flag and interrupt The USART Receiver has one flag that indicates the Receiver state. ^iniEL 7593L-AVR-09/12 187 19.6.4 19.6.5 The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global Inter- rupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter- rupt will occur once the interrupt routine terminates. Receiver error flags The USART Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and Par- ity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buf- fer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags Is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compat- ibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag Is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag Indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait- ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity bit calculation” on page 181 and “Parity Checker” on page 188. Parity Checker The Parity Checker is active when the high USART Parity mode (UPMnI) bit is set. Type of Par- ity Check to be performed (odd or even) is selected by the UPMnO bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 188 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 19.6.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 19.6.7 Flushing the receive buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Assembly code example USART_Flush: sbis UCSRnA, RXCn ret in rl6, UDRn rjmp USART_Flush C code example void USART_Flush ( void ) { unsigned char dummy; while ( UCSRnA & (l«RXCn) } dummy = UDRn ; Note: 1 . See “About code examples” on page 1 0. 19.7 Asynchronous data reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam- ples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 19.7.1 Asynchronous clock recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5 on page 190 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro- cess. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no com- munication activity). 7593L-AVR-09/12 189 Figure 19-5. Start bit sampling. RxD Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam- ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov- ery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. Asynchronous data recovery When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Doubie Speed mode. Figure 19-6 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. IDLE START BITO t thLf t t t f t t I t t t t t f t t t f 001234567 | 8 | 9 | 10 | 11 12 13 14 15 16 1 2 3 t t t t f t f 0 12 3 I 4 I I 5 I I 6 I 7 8 12 Figure 19-6. Sampling of data and parity bit. RxD Sample (U2X = 0) Sample (U2X = 1) X >T hfnf t M f t t t t t t M f t t t t t f t 1 2 3 I 4 I I 5 I I 6 I 7 8 1 The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1 . If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 on page 191 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 19-7. Stop bit sampling and next start bit sampling. RxD Sample (U2X = 0) Sample (U2X = 1) STOP 1 (A) (B) N ^ J ra 0/1 — (C) ^ The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 19-7. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver. 19.7.3 Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 19-2 on page 192) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ^ (Z) + 1 )5 ^ _ (D + 2)5 slow s~^ +D- S + Sp (Z)h-1)5-h5^ D Sum of character size and parity size (D = 5 to 1 0 bit) S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode Sp First sample number used for majority voting. Sp = 8 for normal speed and Sp = 4 for Double Speed mode S|y Middle sample number used for majority voting. Siy = 9 for normal speed and Sy = 5 for Double Speed mode Rsiow is ths I'^tio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate Table 19-2 on page 192 and Table 19-3 on page 192 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. 7593L-AVR-09/12 191 Table 19-2. Recommended maximum receiver baud rate error for Normal Speed mode (U2Xn = 0). D # (Data+Parity Bit) f^slow [°^] Rfast[%] Max. total error [%] Recommended max. receiver error [%] 5 93.20 106.67 -I-6.67/-6.8 ±3.0 6 94.12 105.79 -I-5.79/-5.88 ±2.5 7 94.81 105.11 -i-5.il/-5.19 ±2.0 8 95.36 104.58 -I-4.58/-4.54 ±2.0 9 95.81 104.14 -I-4.14/-4.19 ±1.5 10 96.17 103.78 -I-3.78/-3.83 ±1.5 Table 19-3. Recommended maximum receiver baud rate error for Double Speed mode (U2Xn = 1). D # (Data+Parity Bit) Rslow [%] Rfas. [%] Max. total error [%] Recommended max. receiver error [%] 5 94.12 105.66 +5.66/-5.88 ±2.5 6 94.92 104.92 +4.92/-5.08 ±2.0 7 95.52 104,35 +4.35/-4.48 ±1.5 8 96.00 103.90 +3.90/-4.00 ±1.5 9 96.39 103.53 +3.53/-3.61 ±1.5 10 96.70 103.23 +3.23/-3.30 ±1.0 The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the tempera- ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. 19.8 Multi-processor Communication mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn setting, but has to be used differently when it is a part of a system utilizing the Multi-processor Communication mode. If the Receiver is set up to receive frames that contain five to eight data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames 192 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. 19.8.1 Using MPCMn For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1 ) or cleared when a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1 . All Slave MCUs are In Multi-processor Communication mode (MPCMn in UCSRnA is set). 2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal. 3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the Receiver must change between using n and n-rt character frame formats. This makes full- duplex operation difficult since the Transmitter and Receiver uses the same character size set- ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 19.9 USART register description 19.9.1 UDRn - USART I/O Data Bit Read/write Initial value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg- igister n 7 6 RXB[7:0] TXB[7:0] R/W 0 R/W 0 UDRn (Read) UDRn (Write) R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7593L-AVR-09/12 193 ister (TXB) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit- ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxDn pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify- Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. 19.9.2 UCSRnA - USART Control and Status Register A Bit 7 6 5 4 3 2 1 0 1 RXCn TXCn UDREn FEn □ORn UPEn U2Xn MPCMn 1 UCSRnA Read/write R R/W R R R R R/W R/W Initial value 0 0 1 0 0 0 0 0 • Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit). • Bit 6 - TXCn: USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit). • Bit 5 - UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 - FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 - DORn: Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a 194 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 2 - UPEn: USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMnI = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 1 - U2Xn: Doubie the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication. • Bit 0 - MPCMn: Muiti-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming frames received by the USART Receiver that do not contain address infor- mation will be Ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed information see “Multi-processor Communication mode” on page 192. 19.9.3 UCSRnB - USART Control and Status Register n B Bit 7 6 5 4 3 2 1 0 1 RXCIEn TXCiEn UDRiEn RXENn TXENn UCSZn2 RXBSn TXBSn 1 Read/write R/W R/W R/W R/W R/W R/W R R/W Initial value 0 0 0 0 0 0 0 0 UCSRnB • Bit 7 - RXCiEn: RX Compiete interrupt Enabie n Writing this bit to one enables Interrupt on the RXCn Flag. A USART Receive Complete Interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag In SREG is written to one and the RXCn bit in UCSRnA is set. • Bit 6 - TXCiEn: TX Compiete interrupt Enabie n Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete Interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 - UDRiEn: USART Data Register Empty interrupt Enabie n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only If the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 - RXENn: Receiver Enabie n Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper- ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 - TXENn: Transmitter Enabie n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to 7593L-AVR-09/12 195 zero) will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans- mitted. When disabled, the Transmitter will no longer override the TxDn port. • Bit 2 - UCSZn2: Character Size n The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 1 - RXBSn: Receive Data Bit 8 n RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. • Bit 0 - TXB8n: Transmit Data Bit 8 n TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. 19.9.4 UCSRnC - USART Control and Status Register n C Bit 7 6 5 4 3 2 1 0 1 UMSELnl UMSELnO UPMn1 UPMnO USBSn UCSZnI UCSZnO UCPOLn Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 1 1 0 ] UCSRnC • Bits 7:6 - UMSELnl :0 USART mode select These bits select the mode of operation of the USARTn as shown in Table 19-4. Table 19-4. UMSELn bits settings. UMSELnl UMSELnO Mode 0 0 Asynchronous USART 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM) Note: 1 . See “USART in SPI mode” on page 202 for full description of the Master SPI Mode (MSPIM) operation • Bits 5:4 - UPMnI :0: Parity mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 19-5. UPMn bits settings. UPMnI UPMnO Parity mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, even parity 1 1 Enabled, odd parity 196 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 • Bit 3 - USBSn: Stop Bit select This bit seiects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 19-6. USBS bit settings. USBSn Stop bit(s) 0 1-bit 1 2-bit • Bit 2:1 - UCSZnI :0: Character size The UCSZnI :0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 19-7. UCSZn bits settings. UCSZn2 UCSZnI UCSZnO Character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 - UCPOLn: Clock polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 19-8. UCPOLn bit settings. UCPOLn Transmitted data changed (output of TxDn pin) Received data sampied (input on RxDn pin) 0 Rising XCKn edge Falling XCKn edge 1 Falling XCKn edge Rising XCKn edge 19.9.5 UBRRLn and UBRRHn - USART baud rate registers Bit 15 14 13 12 11 10 9 8 - - - - UBRR[11:8] UBRRHn UBRR[7:0] UBRRLn 7 6 5 4 3 2 1 0 Read/write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7593L-AVR-09/12 197 • Bit 15:12 - Reserved bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 1 1 :0 - UBRR1 1 :0: USART baud rate register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. 19.10 Examples of baud rate setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in Table 19-9 to Table 19-12 on page 201 . UBRR values which yield an actual baud rate differing less than 0.5% from the tar- get baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see “Asynchronous Operational Range” on page 191). The error values are calculated using the fol- lowing equation; Error[%] = BaudRategioges) ^3,^^ Baud Rate • 100 % Table 19-9. Examples of UBRRn settings for commonly used oscillator frequencies. 1.0000MHz = 1.8432MHz = 2.0000MHz Baud rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k - - 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k - - 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k - - - - - - 0 0.0% - - - - 250k - - - - - - - - - - 0 0.0% Max. 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps 1. UBRR = 0, Error =0.0%. 198 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 19-10. Examples of UBRRn settings for commonly used oscillator frequencies. f,,,, = 3.6864MHz fosc = 4.0000MHz f.,,, = 7.3728MHz Baud rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5M - - 0 -7.8% - - 0 0.0% 0 -7.8% 1 -7.8% IM - - - - - - - - - - 0 -7.8% Max. 230.4kbps 460.8kbps 250kbps 0.5Mbps 460.8kbps 921.6kbps 1. UBRR = 0, Error =0.0%. ^IrniU 7593L-AVR-09/12 199 Table 19-11. Examples of UBRRn settings for commonly used oscillator frequencies. fosc = 8.0000MHz = 11.0592MHz fosc = 14.7456MHz Baud rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5M 0 0.0% 1 0.0% - - 2 -7.8% 1 -7.8% 3 -7.8% 1M - - 0 0.0% - - - - 0 -7.8% 1 -7.8% Max. 0.5Mbps 1Mbps 691.2kbps 1 .3824Mbps 921 .6kbps 1 .8432Mbps 1. UBRR = 0, Error =0.0%. 200 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 19-12. Examples of UBRRn settings for commonly used oscillator frequencies. fosc = 16.0000MHz W = 18.4320MHz = 20.0000MHz Baud rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1 .4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1 .4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1 .7% 32 -1 .4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1 .4% 21 -1 .4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1 .4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5M 1 0.0% 3 0.0% - - 4 -7.8% - - 4 0.0% 1M 0 0.0% 1 0.0% - - - - - - - - Max. 1Mbps 2Mbps 1.152Mbps 2.304Mbps 1.25Mbps 2.5Mbps 1. UBRR = 0, Error =0.0%. ^IrniU 7593L-AVR-09/12 201 20. USART in SPI mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow- ing features: • Full duplex, three-wire synchronous data transfer • Master operation • Supports all four SPI modes of operation (Mode 0, 1, 2, and 3) • LSB first or MSB first data transfer (configurable data order) • Queued operation (double buffered) • High resolution baud rate generator • High speed operation (fXCKmax = fCK/2) • Flexible interrupt generation 20.1 Overview Setting both UMSELnl :0 bits to one enables the USART in MSPIM logic. In this mode of opera- tion the SPI master control logic takes direct control over the USART resources. These resources include the transmitter and receiver shift register and buffers, and the baud rate gen- erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both modes of operation. The I/O register locations are the same in both modes. However, some of the functionality of the controi registers changes when using MSPIM. 20.2 Clock generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode of operation only internal clock generation (that is, master operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one (that is, as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 20-1 . Table 20-1 . Equations for calculating baud rate register setting. Operating mode Equation for caicuiating baud rate Equation for caicuiating UBRRn vaiue Synchronous Master mode BAUD = 2{UBRRn + ^) UBRRn = 1 2BAUD Note: 1 . The baud rate is defined to be the transfer rate in bit per second (bps). 202 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 BAUD Baud rate (in bits per second, bps) fosc System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095) 20.3 SPI data modes and timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function- ality is summarized in Tabie 20-2. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. Table 20-2. UCPOLn and UCPHAn functionality. UCPOLn UCPHAn SPI mode Leading edge Trailing edge 0 0 0 Sample (rising) Setup (falling) 0 1 1 Setup (rising) Sample (falling) 1 0 2 Sample (falling) Setup (rising) 1 1 3 Setup (falling) Sample (rising) Figure 20-1 . UCPHAn and UCPOLn data transfer timing diagrams. UCPOL=0 UCPOL=1 II < X Q. O 3 O < X Q. O X XCK Data setup (TXD) _ Data sample (RXD) XCK Data setup (TXD) _ Data sample (RXD) T T T T XCK Data setup (TXD) _ Data sample (RXD) T T T T XCK Data setup (TXD) _ Data sample (RXD) T T 20.4 Frame formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB first A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. 7593L-AVR-09/12 203 16-bit data transfer can be achieved by writing two data bytes to UDRn. A DART transmit com- plete interrupt will then signal that the 16-bit value has been shifted out. 20.4.1 USART MSPIM initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the Receiver. Only the transmitter can operate independently. For interrupt driven USART opera- tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when doing the initialization. Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since UBRRn is reset to zero. Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 204 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Assembly code example USART_Init : clr rl8 out UBRRnH,rl8 out UBRRnL,rl8 ; Setting the XCKn port pin as output, enables master mode, sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0 . Idi rl8, (l«UMSELnl) | (l«UMSELnO) | (0«UCPHAn) | (0«UCPOLn) out UCSRnC,rl8 ; Enable receiver and transmitter. Idi rl8, (l«RXENn) | (l«TXENn) out UCSRnB,rl8 ; Set baud rate . ; IMPORTANT: The Baud Rate must be set after the transmitter is enabled! out UBRRnH, rl7 out UBRRnL, rl8 ret C code example void USART_Init( unsigned int baud ) { UBRRn = 0; /* Setting the XCKn port pin as output, enables master mode. */ XCKn_DDR |= (l«XCKn); /* Set MSPI mode of operation and SPI data mode 0. */ UCSRnC = (l«UMSELnl) | (l«UMSELnO) | (0«UCPHAn) | (0«UCPOLn) ; /* Enable receiver and transmitter. */ UCSRnB = (l«RXENn) | (l«TXENn); /* Set baud rate. */ /* IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRRn = baud ; Note: 1 . See “About code examples” on page 1 0. 20.5 Data transfer Using the USART in MSPI mode requires the Transmitter to be enabled, that is, the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one. When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer clock. ^iniEL 7593L-AVR-09/12 205 After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ- ing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buf- fer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, that is, if an overflow occurs the character last received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte 1 . The following code examples show a simple USART in MSPIM mode transfer function based on polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16 and the data received will be available in the same register (R16) after the function returns. The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. The function then waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value. Assembly code example USART_MSPIM_Transf er : ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (rl6) into buffer, sends the data out UDRn,rl6 ; Wait for data to be received USART_MSPIM_Wait_RXCn : sbis UCSRnA, RXCn rjmp USART_MS P IM_Wa i t_RXCn ; Get and return received data from buffer in rl6, UDRn ret C code example unsigned char USART_Receive ( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (l«UDREn)) ) ; /* Put data into buffer, sends the data */ UDRn = data; /* Wait for data to be received */ while ( ! (UCSRnA & (l«RXCn)) ) ; /* Get and return received data from buffer */ return UDRn; } Note: 1 . See “About code examples” on page 1 0. 206 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 20.5.1 Transmitter and receiver fiags and interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 20.5.2 Disabling the transmitter or receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 20.6 USART MSPIM register description The following section describes the registers used for SPI operation using the USART. 20.6.1 UDRn - USART MSPIM I/O data register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn - USART I/O Data Register n” on page 193. 20.6.2 UCSRnA - USART MSPIM Control and Status Register n A Bit 7 6 5 4 3 2 1 0 1 RXCn TXCn UDREn - - - - 1 Read/write R/W R/W R/W R R R R R Initial value 0 0 0 0 0 1 1 0 UCSRnA • Bit 7 - RXCn: USART receive complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer wiil be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit). • Bit 6 - TXCn: USART transmit complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto- maticaily cieared when a transmit complete interrupt is executed, or it can be cieared by writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit). • Bit 5 - UDREn: USART data register empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4:0 - Reserved bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnA is written. 7593L-AVR-09/12 207 20.6.3 UCSRnB - USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 0 1 RXCIEn TXCIEn UDRIE RXENn TXENn - - 1 Read/write R/W R/W R/W R/W R/W R R R Initial value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete Interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag In SREG is written to one and the RXCn bit in UCSRnA is set. • Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete Interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag In SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 - RXENn: Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the receiver in MSPI mode (that is, setting RXENn=1 and TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. • Bit 3 - TXENn: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans- mitted. When disabled, the Transmitter will no longer override the TxDn port. • Bit 2:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnB is written. 20.6.4 UCSRnC - USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 1 UMSELnl UMSELnO - - - UDORDn UCPHAn UCPOLn 1 Read/write R/W R/W R R R RAW R/W R/W UCSRnC Initial value • Bit 7:6 - UMSELm :0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 20-3 on page 209. See “UCSRnC - USART Control and Status Register n C” on page 1 96 for full description of the nor- 208 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 mal USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled. Table 20-3. UMSELn bits settings. UMSELnl UMSELnO Mode 0 0 Asynchronous USART 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM) • Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 - UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Frame Formats section page 4 for details. • Bit 1 - UCPHAn: Clock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details. • Bit 0- UCPOLn: Clock Polarity The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details. 20.6.5 UBRRnL and UBRRnH - USART MSPIM Baud Rate Registers The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation. See “UBRRLn and UBRRHn - USART baud rate registers” on page 197. 20.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit • The UCPHAn bit functionality is identical to the SPI CPHA bit • The UDORDn bit functionality is identical to the SPI DORD bit However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation is supported by the USART in MSPIM mode, the following features differ between the two modules: • The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer • The USART in MSPIM mode receiver includes an additional buffer level • The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode 7593L-AVR-09/12 209 • The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly • Interrupt timing is not compatible • Pin control differs due to the master only operation of the USART in MSPIM mode A comparison of the USART in MSPIM mode and the SPI pins Is shown in Table 20-4 on page 210. Table 20-4. Comparison of USART in MSPIM mode and SPI pins. USART_MSPIM SPI Comment TxDn MOSI Master Out only RxDn MISO Master In only XCKn SCK (Functionally identical) (N/A) SS Not supported by USART in MSPIM 210 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 21. 2-wire serial interface 21.1 Features • Simple yet powerful and flexible communication interface, only two bus lines needed • Both Master and Slave operation supported • Device can operate as transmitter or receiver • 7-bit address space allows up to 128 different slave addresses • Multi-master arbitration support • Up to 400kHz data transfer speed • Slew-rate limited output drivers • Noise suppression circuitry rejects spikes on bus lines • Fully programmable slave address with general call support • Address recognition causes wake-up when AVR is in sleep mode 21 .2 2-wire Serial Interface bus definition The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard- ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 21-1. TWI bus interconnection. 21.2.1 TWI terminology The following definitions are frequently encountered in this section. Table 21-1. TWI terminology. Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. The Power Reduction TWI bit, PRTWI bit in “PRRO - Power Reduction Register 0” on page 54 must be written to zero to enable the 2-wire Serial Interface. 7593L-AVR-09/12 211 21.2.2 Electrical interconnection As depicted in Figure 21-1 on page 21 1 , both bus lines are connected to the positive supply volt- age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wIred-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices trim-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be pow- ered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical charac- teristics of the TWI is given in “SPI timing characteristics” on page 395. Two different sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz. 21 .3 Data transfer and frame format 21.3.1 Transferring bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 21-2. Data validity. 21.3.2 START and STOP conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relin- quishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SOL line is high. 212 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 21-3. START, REPEATED START and STOP conditions. START STOP START REPEATED START STOP 21 .3.3 Address packet format All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READAA/RITE control bit and an acknowledge bit. If the READAA/RITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas- ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLAh-R or SLAh-W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 21-4. Address packet format. 21 .3.4 Data packet format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and ^iniEL 2" 7593L-AVR-09/12 ® STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 21-5. Data packet format. Aggregate SDA SDA from transmitter SDA from receiver SCL from master SLA+R/W STOP, REPEATED START or next data byte 21 .3.5 Combining address and data packets into a transmission A transmission basically consists of a START condition, a SLA+RAA/, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condi- tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 21-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLAh-R/W and the STOP condition, depending on the software protocol imple- mented by the application software. Figure 21-6. Typical data transmission. 214 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 21.4 Multi-master bus systems, arbitration and synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should Immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted • Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. Figure 21-7. SCL synchronization between multiple masters. SCL from Master A SCL from Master B s \ \ 1 I 1 ' ' 1 1 SCL bus line ^ r 1 1 1 "'"^high Masters start Counting low period \ Masters start Counting high period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one Master remains, and this may take many 7593L-AVR-09/12 215 bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Figure 21-8. Arbitration between two masters. START Master A loses Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composi- tion of SLAh-R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 21 .5 Overview of the TWI module The TWI module is comprised of several submodules, as shown in Figure 21-9 on page 217. All registers drawn in a thick line are accessible through the AVR data bus. 216 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 21-9. Overview of the TWI module. SCL SDA Slew-rate Spike Slew-rate Spike control filter control filter Bus interface unit Bit rate generator START / STOP control Spike suppression Prescaler Arbitration detection Address/data shift register (TWDR) Ack Bit rate register (TWBR) a Address match unit Address register (TWAR) Address comparator Control unit Status register Control register (TWSR) (TWCR) State machine and status control C 13 21.5.1 SCL and SDA pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. 21.5.2 Bit Rate Generator unit This unit controls the period of SCL when operating in a Master mode. The SCL period is con- trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 1 6 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: SCL frequency = CPU Clock frequency TWPS 16-h2(TWBR)-4 • TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register ^iniEL 7593L-AVR-09/12 217 Note: TWBR should be 1 0 or higher if the TWI operates in Master mode. If TWBR is lower than 1 0, the Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob- lem occurs when operating the TWI in Master mode, sending Start -i- SLA -i- RA/V to a Slave (a Slave does not need to be connected to the bus for the condition to happen). 21.5.3 Bus Interface unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controiler and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit aiso contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis- ter is not directiy accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master. If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. 21.5.4 Address Match unit The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sieep mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INTO) occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera- tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. 21.5.5 Control unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta- tus Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is avail- abie. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition • After the TWI has transmitted SLAh-R/W • After the TWI has transmitted an address byte • After the TWI has lost arbitration 218 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 • After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illegal START or STOP condition 21 .6 TWI register description 21.6.1 TWBR - TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 1 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBRO Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TWBR • Bits 7..0 - TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SOL clock frequency in the Master modes. See “Bit Rate Generator unit” on page 217 for calculating bit rates. 21.6.2 TWCR - TWI Control Register Bit 7 6 5 4 3 2 1 0 I TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE I Read/write R/W R/W R/W R/W R R/W R R/W Initial value 0 0 0 0 0 0 0 0 TWCR The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. • Bit 7 - TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the l-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati- cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta- tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. • Bit 6 - TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1 . The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. 7593L-AVR-09/12 219 • Bit 5 - TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 - TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto- matically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SOL and SDA lines to a high impedance state. • Bit 3 - TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. • Bit 2 -TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI Interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SOL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. • Bit 1 - Res: Reserved Bit This bit is a reserved bit and will always read as zero. • Bit 0 - TWIE: TWI Interrupt Enable When this bit is written to one, and the l-bit in SREG is set, the TWI interrupt request will be acti- vated for as long as the TWINT Flag is high. 21.6.3 TWSR - TWI Status Register Bit 7 6 5 4 3 2 1 0 1 TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPSO I Read/write R R R R R R R/W R/W Initial value 1 1 1 1 1 0 0 0 TWSR • Bits 7..3 - TWS: TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described later In this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-blt prescaler value. The application designer should mask the pres- caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 - Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1 ..0 - TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. 220 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 21-2. TWI bit rate prescaler. TWPS1 TWPSO Prescaler value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator unit” on page 217. The value of TWPS1 ..0 Is used in the equation. 21.6.4 TWDR - TWI Data Register Bit 7 6 5 4 3 2 1 0 1 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWDO I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis- ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI Interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7..0 - TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. 21 .6.5 TWAR - TWI (Slave) Address Register Bit 7 6 5 4 3 2 1 0 I TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWAO TWGCE I Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 0 The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters. The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) In the received serial address. If a match is found, an interrupt request is generated. • Bits 7..1 - TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. 7593L-AVR-09/12 221 • Bit 0 - TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 21 .6.6 TWAMR - TWI (Slave) Address Mask Register Bit 7 6 5 4 3 2 1 I TWAM[6:0] Read/write R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 • Bits 7..1 - TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 21-10 shows the address match logic in detail. Figure 21-10. TWI address match logic, block diagram. bitO TWAMRO 1 1 1 Address bit comparator 0 TWARO Address o r> _Address match 0 I TWAMR R 0 Address bit comparator 6..1 • Bit 0 - Res: Reserved Bit This bit is reserved and will always read as zero. 21.7 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should gener- ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus. When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. Figure 21-1 1 on page 223 is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. 222 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 21-11. Interfacing the application to the TWI in a typical transmission. 1 . The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has success- fully been sent. 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the appli- cation software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLAh-W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLAh-W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLAh-W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has success- fully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some spe- cial action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. 7593L-AVR-09/12 223 The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immedi- ately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR Indicates otherwise, the application software might take some spe- cial action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent. Even though this example is simple, it shows the principles Involved In all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT Is cleared • When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C Implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. Assembly code example C example Comments 1 Idi rl6, (1«TWINT) 1 (1«TWSTA) | (1«TWEN) out TWCR, rl6 TWCR = (1«TWINT) (1«TWSTA) (1«TWEN) Send START condition 2 waitl : in r 16, TWCR sbrs r 16, TWINT rjmp waitl while ( ! (TWCR & (1< < > PAGEL tevPH tpLBX tevwL twLBX WR tpLWL WLRL / RDY/BSY ^WLRH Figure 30-8. Parallel programming timing, loading sequence with timing requirements LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) PAG EL DATA APPRO (Low byte) ^ DATA (Low byte) XAO DATA (High byte) X ADDR1 (Low byte) XA1 Note: 1 . The timing requirements shown in Figure 30-7 (that is, tpy^H’ ^xhxL’ ^xldx) ^PPlV loading operation. Figure 30-9. Parallel programming timing, reading sequence (within the same page) with tim- ing requirements LOAD ADDRESS (LOW BYTE) READ DATA READ DATA (LOW BYTE) (HIGH BYTE) LOAD ADDRESS (LOW BYTE) XAO XA1 X. 372 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Note: 1 . The timing requirements shown in Figure 30-7 (that is, t^^xH- *xhxL’ txLox) ^'so appiy to reading operation. Table 30-13. Parallel programming characteristics, Vqq = 5V ±10%. Symbol Parameter Min. Typ. Max. Units Vpp Programming Enable Voltage 11.5 12.5 V Ipp Programming Enable Current 250 pA toVXH Data and Control Valid before XTAL1 High 67 ns fxLXH XTAL1 Low to XTAL1 High 200 fxHXL XTAL1 Pulse Width High 150 *XLDX Data and Control Hold after XTAL1 Low 67 fxLWL XTAL1 Low to WR Low 0 *XLPH XTAL1 Low to PAGEL high 0 fpLXH PAGEL low to XTAL1 high 150 fsVPH BS1 Valid before PAGEL High 67 fpHPL PAGEL Pulse Width High 150 fpLBX BS1 Hold after PAGEL Low 67 fwLBX BS2/1 Hold after WR Low 67 fpLWL PAGEL Low to WR Low 67 Ibvwl BS2/1 Valid to WR Low 67 fwLWH WR Pulse Width Low 150 twLRL WR Low to RDY/BSY Low 0 1 ps *WLRH WR Low to RDY/BSY High 3.7 4.5 ms fwLRH_CE WR Low to RDY/BSY High for Chip Erase 7.5 9 *XLOL XTAL1 Low to OE Low 0 ns fBVDV BS1 Valid to DATA valid 0 250 toLDV OE Low to DATA Valid 250 toHDZ OE High to DATA Tri-stated 250 Notes: 1 . ty^Lpm is valid for the Write Fiash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tyvLRH CE is vaiid for the Chip Erase command. 30.7 Serial downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI (input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 30-14 on page 374, the pin mapping for serial programming is listed. Not all packages use the SPI pins dedicated for the internal Serial Peripheral Interface - SPI. 7593L-AVR-09/12 373 30.8 Serial programming pin mapping Table 30-14. Pin mapping serial programming. Symbol Pins (TQFP-64) I/O Description PDI PB2 1 Serial Data in PDO PB3 0 Serial Data out SCK PB1 1 Serial Clock Figure 30-10. Serial programming and verify Notes: 1 . If the device is clocked by the internal Oscillator, it is no need to connect a ciock source to the XTAL1 pin. 2. Vqq - 0.3V < AVCC < Vqq + 0.3V, however, AVCC should always be within 1 .8 - 5.5V. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into OxFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f^k < 12MHz, 3 CPU clock cycles for f^^ >= 12MHz High: > 2 CPU clock cycles for f^k < 1 2MHz, 3 CPU clock cycles for f^k >= 1 2MHz 30.8.1 Serial programming algorithm When writing serial data to the Atmel AT90USB64/128, data is clocked on the rising edge of SCK. When reading data from the AT90USB64/128, data is clocked on the falling edge of SCK. See Figure 30-1 1 on page 375 for timing details. To program and verify the AT90USB64/128 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 30-16 on page 376): 1 . Power-up sequence: Apply power between Vqq and GND while RESET and SCK are set to “0”. In some sys- tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin PDI. 374 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 3. The serial programming instructions will not work if the communication is out of syn- chronization. When in sync, the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the address lines 15. .8. Before issuing this command, make sure the instruction Load Extended Address Byte has been used to define the MSB of the address. The extended address byte is stored until the command is re-issued, i.e., the command needs only be issued for the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not used, the user must wait at least t^D pL^sH before issuing the next page. (See Table 30- 15.) Accessing the serial programming interface before the Flash write operation com- pletes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t^o pEppioM before issuing the next byte. (See Table 30-15.) In a chip erased device, no OxFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output PDO. When reading the Flash memory, use the instruction Load Extended Address Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the 64KWord boundary. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn Vqq power off. Table 30-15. Minimum wait delay before writing the next Flash or EEPROM location. Symbol Minimum wait deiay twD_FLASH 4.5ms twD_EEPROM 9.0ms twD_ERASE 9.0ms Figure 30-11. Serial programming waveforms. SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE I I I t t f t t t t t 7593L-AVR-09/12 ^imlL 375 Table 30-16. Serial programming instruction set. Instruction Instruction format Operation Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 10 Ox xxxx xxxx XXXX xxxx xxxx Chip Erase EEPROM and Flash. Load Extended Address Byte 0100 1101 0000 0000 CCCC CCCC xxxx xxxx Defines Extended Address Byte for Read Program Memory and Write Program Memory Page. Read Program Memory 0010 HOOO aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address c:a:b. Load Program Memory Page 0100 HOOO xxxx xxxx xxbb bbbb iiii iiii Write H (high or iow) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page 0100 1100 aaaa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at address c:a:b. Read EEPROM Memory 1010 0000 0000 aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. Write EEPROM Memory 1100 0000 0000 aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 OObb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. Write EEPROM Memory Page (page access) 1100 0010 0000 aaaa bbbb bbOO xxxx xxxx Write EEPROM page at address a:b. Read Lock bits 0101 1000 0000 0000 XXXX xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 30-1 on page 359 for details. Write Lock bits 1010 1100 11 lx xxxx xxxx xxxx Iiii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 30-1 on page 359 for details. Read Signature Byte 0011 0000 00 Ox xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 30-3 on page 360 for details. Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” = unprogrammed. Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro- grammed, “1” = unprogrammed. 376 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 30-16. Serial programming instruction set. (Continued) Instruction Instruction format Operation Byte 1 Byte 2 Bytes Byte 4 Read Extended Fuse Bits 0101 0000 0000 1000 XXXX XXXX oooo oooo Read Extended Fuse bits. “0” = pro- grammed, “1” = unprogrammed. See Table 30-3 on page 360 for details. Read Calibration Byte 0011 1000 00 Ox xxxx 0000 0000 oooo oooo Read Calibration Byte Poli RDY/BSY 1111 0000 0000 0000 xxxx XXXX xxxx xxxo If o = “1”, a programming operation is still busy. Wait until this bit returns to “0” before applying another command. Note: a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in. X = don’t care. 30.8.2 Serial programming characteristics For characteristics of the Serial Programming module see “SPI timing characteristics” on page 395. 30.9 Programming via the JTAG interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys- tem Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded- icated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum fre- quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. 30.9.1 Programming specific JTAG instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 30-12 on page 378. 7593L-AVR-09/12 377 Figure 30-12. State machine sequence for changing the instruction word. 30.9.2 AVR_RESET (OxC) The AVR specific pubiic JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controiier is not reset by this instruction. The one bit Reset Register is seiected as Data Register. Note that the reset wiii be active as iong as there is a iogic “one” in the Reset Chain. The output from this chain is not iatched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input 30.9.3 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16- bit Programming Enable Register is selected as Data Register. The active states are the following: • Shift-DR: The programming enable signature is shifted into the Data Register • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid 378 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 30.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command 30.9.5 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the eight LSBs of the Programming Command Register. The active states are the following: • Shift-DR: The Flash Data Byte Register is shifted by the TCK input • Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence is initiated that within 1 1 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incriminated before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter increment into the next page 30.9.6 PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page • Shift-DR: The Flash Data Byte Register is shifted by the TCK input 30.9.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Pro- gramming specific JTAG instructions” on page 377. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 7593L-AVR-09/12 379 30.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock sources” on page 41) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 9-1 on page 58. 30.9.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_001 1_01 1 1_0000. When the con- tents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 30-13. Programming enable register. TOO 30.9.10 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 30-17 on page 382. The state sequence when shifting in the programming commands is illustrated in Figure 30-15 on page 385. 380 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 30-14. Programming Command register. Flash EEPROM fuses lock bits 7593L-AVR-09/12 ® 381 Table 30-17. JTAG programming instruction set. a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 1a. Chip Erase 0100011_10000000 oil 0001_1 0000000 oil 001 1_1 0000000 oil 001 1_1 0000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1 b. Foil for Chip Erase Complete oil 001 1_1 0000000 xxxxxox_xxxxxxxx (2) 2a. Enter Flash Write 010001 1_0001 0000 xxxxxxx_xxxxxxxx 2b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 2c. Load Address High Byte 00001 11 _aaaaaaaa xxxxxxx_xxxxxxxx 2d. Load Address Low Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 2e. Load Data Low Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx 2f. Load Data High Byte OOlomjiiiiiii xxxxxxx_xxxxxxxx 2g. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. Write Fiash Page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. Foil for Page Write Compiete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. Enter Flash Read 010001 1_00000010 xxxxxxx_xxxxxxxx 3b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 3c. Load Address High Byte 00001 1 1_aaaaaaaa xxxxxxx_xxxxxxxx 3d. Load Address Low Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 3e. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo Low byte High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 00001 1 1_aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. Load Address Low Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. Write EEPROM Page 0110011_00000000 oil 0001 _00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 382 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 30-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 4g. Poli for Page Write Complete 011001 1_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 00001 11 _aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. Load Address Low Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 6a. Enter Fuse Write 010001 1_01 000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. Poli for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse High Byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. Poli for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6h. Load Data Low Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx (3) 6i. Write Fuse Low Byte 0110011_00000000 oil 0001 _00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. Foil for Fuse Write Compiete 0110011_00000000 xxxxxox_xxxxxxxx (2) 7a. Enter Lock Bit Write 010001 1_00100000 xxxxxxx_xxxxxxxx 7b. Load Data Byte OOlOOlIJiiiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock Bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. Poli for Lock Bit Write compiete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. Enter Fuse/Lock Bit Read 010001 1_000001 00 xxxxxxx_xxxxxxxx 8b. Read Extended Fuse Byte 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. Read Fuse High Byte 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 7593L-AVR-09/12 383 Table 30-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 8d. Read Fuse Low Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 0111010_00000000 xxxxxxx_xxxxxxxx (5) 0111110_00000000 xxxxxxx_oooooooo Fuse Ext. byte 8f. Read Fuses and Lock Bits 0110010_00000000 xxxxxxx_oooooooo Fuse High byte 0110110_00000000 xxxxxxx_oooooooo Fuse Low byte 0110111_00000000 xxxxxxx_oooooooo Lock bits 9a. Enter Signature Byte Read 010001 1_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 010001 1_00001 000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 000001 1_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Notes: 1 . This command sequence is not required if the seven MSB are correctiy set by the previous command sequence (which is normaily the case). 2. Repeat until o = “1”. 3. Set bits to “0” to program the corresponding Fuse, “1” to un-program the Fuse. 4. Set bits to “0” to program the corresponding Lock bit, “1” to ieave the Lock bit unchanged. 5. “0” = programmed, “1” = un-programmed. 6. The bit mapping for Fuses Extended byte is iisted in Tabie 30-3 on page 360. 7. The bit mapping for Fuses High byte is iisted in Table 30-4 on page 361 . 8. The bit mapping for Fuses Low byte is iisted in Table 30-5 on page 361 . 9. The bit mapping for Lock bits byte is listed in Table 30-1 on page 359. 10. Address bits exceeding PCMSB and EEAMSB (Table 30-1 1 on page 364 and Table 30-12 on page 365) are don’t care. 1 1 . All TDI and TOO sequences are represented by binary digits (Ob...). 384 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 30-15. State machine sequence for changing/reading the data word. 30.9.1 1 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read oul/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out. The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. During page load, the Update-DR state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 1 1 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the Program Counter increment into the next page. During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap- ^iniEL 7593L-AVR-09/12 385 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 30-16. Flash Data Byte Register. TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis- ter with sufficient number of clock pulses to complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at least 1 1 TCK cycles between each Update-DR state. 30.9.12 Programming algorithm All references below of type “la”, “1b”, and so on, refer to Table 30-17 on page 382. 30.9.13 Entering Programming mode 1 . Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 0b1010_0011_01 11_0000 in the Program- ming Enable Register. 30.9.14 Leaving Programming mode 1 . Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program- ming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 386 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 30.9.15 Performing Chip Erase 1 . Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction la. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for twLRH_cE (refer to Table 30-1 3 on page 373). 30.9.16 Programming the Fiash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 387. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6. Load data using programming instructions 2e, 2f and 2g. 7. Repeat steps 5 and 6 for all instruction words in the page. 8. Write the page using programming instruction 2h. 9. Poll for Flash write complete using programming instruction 2i, or wait for (refer to Table 30-13 on page 373). 10. Repeat steps 3 to 9 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_P AGELOAD instruction: 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b, 2c and 2d. PCWORD (refer to Table 30-1 1 on page 364) is used to address within one page and must be written as 0 . 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page byte-by-byte, start- ing with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte Register into the Flash page location and to auto-increment the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2h. 8. Poll for Flash write complete using programming instruction 2i, or wait for t^vLRH (refer to Table 30-13 on page 373). 9. Repeat steps 3 to 8 until all data have been programmed. 30.9.17 Reading the Flash 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b, 3c and 3d. 4. Read data using programming instruction 3e. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 7593L-AVR-09/12 387 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 30-1 1 on page 364) is used to address within one page and must be written as 0 . 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 30.9.18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip Erase” on page 387. 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for t^LRH (refer to Table 30-1 3 on page 373). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 30.9.19 Reading the EEPROM 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM. 30.9.20 Programming the Fuses 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will un-program the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for t^^LPH (refer to Table 30-13 on page 373). 388 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for t^^LPH (refer to Table 30-13 on page 373). 30.9.21 Programming the Lock Bits 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corre- sponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for t^LPH (refer to Table 30-13 on page 373). 30.9.22 Reading the Fuses and Lock Bits 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. 30.9.23 Reading the Signature Bytes 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 30.9.24 Reading the Caiibration Byte 1 . Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. 7593L-AVR-09/12 389 31. Electrical characteristics for Atmel AT90USB64/1 28 31.1 Absolute maximum ratings* Operating temperature -40°C to +85°C Storage temperature -65°C to +150°C Voltage on any pin except RESET and VBUS with respect to ground -0.5V to Vqq+0.5V Voltage on RESET with respect to ground -0.5V to +13.0V Voltage on VBUS with respect to ground -0.5V to -1-6.OV Maximum operating voltage -1-6. OV DC current per I/O pin 40.0mA DC current Vqq and GND pins 200.0mA ‘NOTICE: Stresses beyond those listed under “Absolute maximum ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 31 .2 DC characteristics Ta = -40°C to 85°C, Vqc = 2.7V to 5.5V (unless otherwise noted). Symbol Parameter Condition Min. (®> Typ. Max. Units V|L Input Low Voltage, Except XTAL1 and Reset pin Vcc = 2.7V - 5.5V -0.5 0 .2 Vqq(') V V|L1 Input Low Voltage, XTAL1 pin Vcc = 2.7V - 5.5V -0.5 0.1 Vqq V|L2 Input Low Voltage, RESET pin Vcc = 2.7V - 5.5V -0.5 O.IVqq(') V|H Input High Voltage, Except XTAL1 and RESET pins Vcc = 2.7V - 5.5V 0 .6 Vqc<2 ) Vcc + V|H1 Input High Voltage, XTAL1 pin Vcc = 2.7V - 5.5V 0.7Vqc<2) Vcc + 0-5 V|H2 Input High Voltage, RESET pin Vcc = 2.7V - 5.5V 0.9Vqc<2) Vcc + _l 0 > Output Low Voltage ® loL = 10mA, Vcc = 5V Iql = 5mA, Vqq = 3V 0.3 0.2 0.7 0.5 X 0 > Output High Voltage 0 0 X X II II ro 0 0 3 3 > > < < 0 0 0 0 II II CO cn < < 4.2 2.3 4.5 2.6 l|L Input Leakage Current I/O Pin Vqq = 5.5V, pin low (absolute value) 1 pA l|H Input Leakage Current I/O Pin Vqq = 5.5V, pin high (absolute value) 1 FIrst Reset Pull-up Resistor 30 60 kn F*PU I/O Pin Pull-up Resistor 20 50 390 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 = -40°C to 85°C, Vqq = 2.7V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition Min. Typ. Max. Units 'cc Power Supply Current Active 4MHz, Vqq = 3V (AT90USB64/128) 2.5 5 mA Active 8MHz, Vqq = 3V (AT90USB64/128) 5 10 Active 8MHz, Vqq = 5V (AT90USB64/128) 10 18 Active 16MHz, Vqq = 5V (AT90USB64/128) 19 30 Icc Power-down mode WDT enabled, BOD enabled, Vqq = 3V, 25°C 30 pA WDT enabled, BOD disabled, Vqq = 3V, 25°C 10 WDT disabled, BOD disabled, Vqq = 3V, 25°C 2 Vac 10 Analog Comparator Input Offset Voltage Vqq = 5V vr=Voo/2 10 40 mV UcLK Analog Comparator Input Leakage Current Vqq = 5V Vin = Vcc/2 -50 50 nA WiD Analog Comparator Propagation Delay Vqq = 2.7V Vcc = 4.0V 750 500 ns Iq USB Regulator Quiescent Current UVqc >3.6V, I = 0mA 10 30 pA Vusb USB Regulator Output Voltage (Ucap) UVqc >3.6V, I = 40mA 3.0 3.3 3.5 V Note: 1 . "Max" means the highest value where the pin is guaranteed to be read as iow 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at V^q = 5V, 10mA at Vqq = 3V) under steady state conditions (non-transient), the following must be observed: Atmel AT90USB64/128: 1 .)The sum of all lOL, for ports A0-A7, G2, C4-C7 should not exceed 100mA. 2. )The sum of all lOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA. 3. )The sum of all lOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA. 4. )The sum of all lOL, for ports F0-F7 should not exceed 100mA. If lOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at Vqq = 5V, 1 0mA at Vqq = 3V) under steady state conditions (non-transient), the following must be observed: AT90USB64/128: 1) The sum of all lOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA. 2) The sum of all lOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA. 3) The sum of all lOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA. 4) The sum of all lOH, for ports F0-F7 should not exceed 100mA. 5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcon- trollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon 6. Values with “PRR1 - Power Reduction Register 1” disabled (0x00). 7593L-AVR-09/12 391 7. As specified on the USB Eiectrical chapter of USB Specifications 2.0, the D+/D- pads can withstand voitages down to -1 V appiied through a 39Q resistor 8. USB Peripherai consumes up to 50mA from the reguiator or UVqq pin when USB is used at full-load 31 .3 External clock drive waveforms Figure 31-1. External clock drive waveforms. 31 .4 External clock drive Table 31-1. External clock drive. Symbol Parameter Vcc=1.8-5.5V Vcc=2.7-5.5V Vcc=4.5-5.5V Units Min. Max. Min. Max. Min. Max. l/tcLCL Oscillator Frequency 0 2 0 8 0 16 MHz *CLCL Clock Period 500 125 62.5 ns 'CHCX High Time 200 50 25 'CLCX Low Time 200 50 25 *CLCH Rise Time 2.0 1.6 0.5 ps ^CHCL Fall Time 2.0 1.6 0.5 ^^CLCL Change in period from one clock cycle to the next 2 2 2 % Note: All DC characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are pre- liminary values representing design targets, and will be updated after characterization of actual silicon. 31.5 Maximum speed vs. Maximum frequency is depending on Vqq As shown in Figure 31-2 on page 393, the maximum frequency vs. Vqq curve is linear between 2.7V < Vqq < 5.5V. 392 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 31-2. Maximum frequency vs. Vqq, Atmel AT90USB64/128. 31 .6 2-wire serial interface characteristics Table 31-2 describes the requirements for devices connected to the 2-wire Serial Bus. The AT90USB64/128 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbois refer to Figure 31-3 on page 394. Table 31-2. 2-wire serial bus requirements. Symbol Parameter Condition Min Max Units VIL Input Low-voltage -0.5 0.3 Vqq V VIH Input High-voltage 0.7 Vcc Vcc + 0.5 Vhys<^> Hysteresis of Schmitt Trigger Inputs 0.05 Vcc - VOL<^> Output Low-voltage 3mA sink current 0 0.4 Rise Time for both SDA and SCL 20 + 0.1Cb<®><^> 300 ns Output Fall Time from V|H„ip to 10pF max(16fscL, 250kHz) 0 400 kHz Rp Value of Pull-up resistor fscL^ 100kHz Fee -0.4V 1000ns n 3mA Ct fscL> 100kHz Fee -0.4V 300ns 3mA Cb ^iniEL 7593L-AVR-09/12 393 Table 31-2. 2-wire serial bus requirements. (Continued) Symbol Parameter Condition Min Max Units thDiSTA Hold Time (repeated) START Condition fgQL < 100kHz 4.0 - fggL> 100kHz 0.6 - trow Low Period of the SCL Clock fgQL < 100kHz <®) 4.7 - fgQL > 100kHz 1.3 - tuiGH High period of the SCL clock fgQL < 100kHz 4.0 - ps fggL> 100kHz 0.6 - tsU;STA Set-up time for a repeated START fgQL < 100kHz 4.7 - condition fggL> 100kHz 0.6 - thDiDAT Data hold time fgQL < 100kHz 0 3.45 fggL> 100kHz 0 0.9 tsU;DAT Data setup time fgQL < 100kHz 250 - ns fggL> 100kHz 100 - tsU;STO Setup time for STOP condition fgQL < 100kHz 4.0 - fggL> 100kHz 0.6 - ps tsUF Bus free time between a STOP and fgQL < 100kHz 4.7 - START condition fggL> 100kHz 1.3 - Notes: 1 . In Atmel AT90USB64/128, this parameter is characterized and not 100% tested. 2. Required only for fgQL >100kHz. 3. C |3 = capacitance of one bus line in pF. 4. fpK = CPU clock frequency 5. This requirement applies to all AT90USB64/1 28 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fgQL requirement. 6. The actual low period generated by the AT90USB64/128 2-wlre Serial Interface Is (1/fscL - 2/fcK), thus fg^ must be greater than eiVIHz for the low time requirement to be strictly met at fgQL = 100kHz. 7. The actual low period generated by the AT90USB64/128 2-wlre Serial Interface Is (1/fsQL - S/fg^), thus the low time require- ment will not be strictly met for fggL > 308kHz when fg^ = 8IVIHz. Still, AT90USB64/128 devices connected to the bus may communicate at full speed (400kHz) with other AT90USB64/128 devices, as well as any other device with a proper Ilow acceptance margin. Figure 31-3. 2-wire serial bus timing. 394 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 31.7 SPI timing characteristics See Figure 31-4 and Figure 31-5 on page 396 for details. Table 31-3. SPI timing parameters. Description Mode Min. Typ. Max. 1 SCK period Master See Table 18-4 on page 1 74 2 SCK high/low Master 50% duty cycle 3 Rise/Fali time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 X tg^k ns 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS iow to out Slave 15 10 SCK period Slave 4xtck 11 SCK high/iow Slave 2xt^k 12 Rise/Faii time Slave 1.6 ps 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 ns 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 Note: 1 . In SPI Programming mode the minimum SCK high/low period is: ■ 2 tcLCL ^CK <12IVIHz - 3 tQLcL tO’’ tcK >12MHz Figure 31-4. SPI interface timing requirements (master mode). SS ^iniEL e 7593L-AVR-09/12 395 Figure 31-5. SPI interface timing requirements (slave mode). 31 .8 Hardware boot entrance timing characteristics Figure 31-6. Hardware boot timing requirements. RESET ^SHRH ALE/HWB — — — — — — *HHRH Tabie 31-4. Hardware boot timings. Symbol Parameter Min. Max. tSHRH HWB low Setup before Reset High 0 tHHRH HWB low Hold after Reset High StartUpTime (SUT) + Time Out Delay (TOUT) 396 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 31 .9 ADC characteristics Table 31-5. ADC characteristics. Symbol Parameter Condition Min. Typ. Max. Units Resolution Single Ended Conversion 10 Bits Differential Conversion Gain = 1x or 10x 8 Differential Conversion Gain = 200x 7 Absolute accuracy (Including iNL, DNL, quantization error, gain and offset error) Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz 1.5 LSB Single Ended Conversion ^REF = 4V, Vqq = 4V, ADC clock = IMHz Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz Noise Reduction Mode 1.5 Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 1MHz Noise Reduction Mode Absolute accuracy Gain = 1x, 10x, 200x Vref = 4V, Vcc = 5V ADC Clock = 50 - 200kHz 1 Integral Non-Linearity (INL) Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz 0.5 1 Integral Non-Linearity (INL) (Accuracy after calibration for offset and gain error) Gain = 1x, 10x, 200x Vref = 4V, Vcc = 5V ADC Clock = 50 - 200kHz 0.5 1 Differential Non-Linearity (DNL) Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz 0.3 1 Gain Error Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz -2 0 -f2 Gain = 1x, 10x, 200x -2 0 -f2 Offset Error Single Ended Conversion Vref = 4V, Vcc = 4V, ADC clock = 200kHz -2 1 -f2 Gain = 1x, 10x, 200x Vref = 4V, Vcc = 5V ADC Clock = 50 - 200kHz -1 0 -Fl Conversion Time Free Running Conversion 65 260 MS Clock Frequency Single Ended Conversion 50 1000 kHz ^iniEL 7593L-AVR-09/12 397 Table 31-5. ADC characteristics. (Continued) Symbol Parameter Condition Min. Typ. Max. Units AVCC Analog Supply Voltage CO d o o > ^cc V ^REF Reference Voltage Single Ended Conversion 2.0 AVCC Differential Conversion 2.0 AVCC - 0.5 V|N Input Voltage Single ended channels 0 Vref Differential Conversion 0 AVCC Input Bandwidth Single Ended Channels 38,5 kHz Differential Channels 4 ^INT1 Internal Voltage Reference 1.1V 1.0 1.1 1.2 V V|NT2 Internal Voltage Reference 2.56V 2.4 2.56 2.8 F*ref Reference Input Resistance 32 kn Rain Analog Input Resistance 100 Mn 398 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 31.10 External data memory timing Table 31-6. External data memory characteristics, 4.5 - 5.5 Volts, no wait-state. 8MHz oscillator Variable oscillator Symbol Parameter Min. Max. Min. Max. Unit 0 1 ^'CLCL Oscillator Frequency 0.0 16 MHz 1 tlHLL ALE Pulse Width 115 1 -O^CLCL'I 0 2 UvLL Address Valid A to ALE Low 57.5 0.5tcLCL-5 <'> 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b 'llax_ld Address Hold after ALE Low, read access 5 5 4 UvLLC Address Valid C to ALE Low 57.5 0.5tcLCL-5 <'> 5 Wrl Address Valid to RD Low 115 1 -O^CLCL'I 0 6 UvWL Address Valid to WR Low 115 1 -O^CLCL'I 0 7 ^LLWL ALE Low to WR Low 47.5 67.5 0.5tcLCL-15<"> 0.5tcLCL+5 <"> ns 8 I^LLRL ALE Low to RD Low 47.5 67.5 0.5tcLCL-15<"> 0.5tcLCL+5 9 ^DVRH Data Setup to RD High 40 40 10 ^RLDV Read Low to Data Valid 75 ^ -OtcLCL'SO 11 ^RHDX Data Hold After RD High 0 0 12 ^RLRH RD Pulse Width 115 1 -O^CLCL'I 0 13 ^DVWL Data Setup to WR Low 42.5 0.5tcLCL-20 <'> 14 ^WHDX Data Hold After WR High 115 ^ -O^CLCL"^ 0 15 ^DVWH Data Valid to WR High 125 1 -O^CLCL 16 ^WLWH WR Pulse Width 115 ^ -O^CLCL"^ 0 Notes: 1 . This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1 . 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1 . Table 31-7. External data memory characteristics, 4.5 - 5.5 Volts, 1 cycle wait-state. Symbol Parameter 8MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1/^CLCL Oscillator Frequency 0.0 16 MHz 10 ^RLDV Read Low to Data Valid 200 2-0toLCL‘50 ns 12 ^RLRH RD Pulse Width 240 2-0tQLQL-1 0 15 ^DVWH Data Valid to WR High 240 2-OtcLCL 16 'WLWH WR Pulse Width 240 2-0tQLQL-1 0 7593L-AVR-09/12 399 Table 31-8. External data memory characteristics, 4.5 - 5.5 Volts, SRWnI = 1 , SRWnO = 0. Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1 '^'CLCL Oscillator Frequency 0.0 16 MHz 10 ^RLDV Read Low to Data Valid 325 3-0tQLQL-50 ns 12 ^RLRH RD Pulse Width 365 ^■OtcLCL"^ 0 15 ^DVWH Data Valid to WR High 375 3-OtcLCL 16 ^WLWH WR Pulse Width 365 3-0tQLQL-1 0 Table 31-9. External data memory characteristics, 4.5 - 5.5 Volts, SRWnI = 1 , SRWnO = 1 . Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1 /^CLCL Oscillator Frequency 0.0 16 MHz 10 ^RLDV Read Low to Data Valid 325 3-0^clcl‘50 ns 12 ^RLRH RD Pulse Width 365 ^■OtcLCL"^ 0 14 'WHDX Data Hold After WR High 240 2-0tcLCL‘^ 0 15 ^DVWH Data Valid to WR High 375 3-OtcLCL 16 ^WLWH WR Pulse Width 365 3-0tQLQL-1 0 Table 31-10. External data memory characteristics, 2.7 - 5.5 Volts, no wait-state. 4MHz oscillator Variable oscillator Symbol Parameter Min. Max. Min. Max. Unit 0 1 '^^CLCL Oscillator Frequency 0.0 8 MHz 1 ^LMLl ALE Pulse Width 235 ^clcl‘15 2 Wll Address Valid A to ALE Low 115 0.5tcLCL-10<') 3a ^LLAX_ST Address Hold After ALE Low, write access 5 5 3b ^LLAX_LD Address Hold after ALE Low, read access 5 5 4 UvLLC Address Valid 0 to ALE Low 115 0.5tcLCL-10<'' 5 Wrl Address Valid to RD Low 235 ^ -O^CLCL"^ 5 ns 6 WwL Address Valid to WR Low 235 1 -O^CLCL'^ 5 7 ^LLWL ALE Low to WR Low 115 130 0.5tcLCL-10<"> 0.5tcLCL+5 8 ^LIRL ALE Low to RD Low 115 130 0.5tcLCL-10<"» 0.5tcLCL+5 9 ^DVRH Data Setup to RD High 45 45 10 ^RLDV Read Low to Data Valid 190 ^ -O^CLCL"®® 11 ^RHDX Data Hold After RD High 0 0 400 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Table 31-10. External data memory characteristics, 2.7 - 5.5 Volts, no wait-state. (Continued) Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 12 ^RLRH RD Pulse Width 235 ^ -O^CLCL"^ 5 ns 13 ^DVWL Data Setup to WR Low 105 0.5tcLCL-20 14 ^WHDX Data Hold After WR High 235 1 -O^CLCL'^ 5 15 ^DVWH Data Valid to WR High 250 1 -O^CLCL 16 ^WLWH WR Pulse Width 235 1 -O^CLCL'^ 5 Notes: 1 . This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1 . 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1 . Table 31-11. External data memory characteristics, 2.7 - 5.5 Volts, SRWnI = 0, SRWnO = 1. Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1'^^CLCL Oscillator Frequency 0.0 8 MHz 10 ^RLDV Read Low to Data Valid 440 2-0toLCL‘60 ns 12 ^RLRH RD Pulse Width 485 2-0tQLQL-1 5 15 ^DVWH Data Valid to WR High 500 2-OtcLCL 16 'WLWH WR Pulse Width 485 2-0tQLQL-1 5 Table 31-12. External data memory characteristics, 2.7 - 5.5 Volts, SRWnI = 1, SRWnO = 0. Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1 ^'CLCL Oscillator Frequency 0.0 8 MHz 10 ^RLDV Read Low to Data Valid 690 3-0tcLCL‘60 ns 12 ^RLRH RD Pulse Width 735 3-0tQLQL-1 5 15 ^DVWH Data Valid to WR High 750 3-OtcLCL 16 'WLWH WR Pulse Width 735 2-0tQLQL-1 5 Table 31-13. External data memory characteristics, 2.7 - 5.5 Volts, SRWnI = 1 , SRWnO = 1 . Symbol Parameter 4MHz oscillator Variable oscillator Unit Min. Max. Min. Max. 0 1'^^CLCL Oscillator Frequency 0.0 8 MHz 10 ^RLDV Read Low to Data Valid 690 3-0tQLQL-60 ns 12 ^RLRH RD Pulse Width 735 3-0tQLQL-1 5 14 ^WHDX Data Hold After WR High 485 2-0tQLQL-1 5 15 ^DVWH Data Valid to WR High 750 3-OtcLCL 16 'WLWH WR Pulse Width 735 2-0tQLQL-1 5 7593L-AVR-09/12 401 ^imlL Figure 31-7. External memory timing (SRWnI = 0, SRWnO = 0. T1 I T2 I T3 I T4 I A / \ / \ / \ ^ i / ^ System clock (CLK^pu) A15:8 Prev. addr. DA7:0 Prdv. data DA7:0 (XMBK = 0) )C X V r ^ a — c A / Figure 31-8. External memory timing (SRWnI = 0, SRWnO = 1). I T1 I T2 I T3 I T4 , T5 , System clock (CLK^^py) j. \ / \ t \ i \ i A15:8 Prev. addr. DA7:0 Pr^v. data DA7:0 (XMBK = 0) )C A A M. f X t r c 402 AT90USB64/128 7593L-AVR-09/12 Read Write Read Write AT90USB64/128 Figure 31-9. External memory timing (SRWnI = 1 , SRWnO = 0). T1 I T2 I T3 I ^T4 ^ T5 , T6 , System clock (CLKcpy) i w A15:8 Prev. addr. DA7:0 Pr6v. data DA7:0(XMBK = 0) • IL 13 L I Data V Addres! ;"^ 1 1 8 X f X t a r Figure 31-10. External memory timing (SRWnI = 1, SRWnO = 1). System clock (CLK^pu) DA7:0(XMBK = 0) The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external). ^imlL 7593L-AVR-09/12 403 Read Write 32. Atmel AT90USB64/1 28 typical characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR regis- ters set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera- ture. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as Ci^xV^cXf where Cl = load capacitance, Vqq = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential cur- rent drawn by the Watchdog Timer. 404 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 32.1 Input voltage levels Figure 32-1. Input low voltage vs. Vqc, all I/Os excluding DP/DM, XTAL1 and reset. Vcc(V) Figure 32-2. Input high voltage vs. Vqq, all I/Os excluding DP/DM, XTAL1 and reset. Vcc(V) ^rniEL 7593L-AVR-09/12 405 32.2 Output voltage levels Figure 32-3. Output low voltage vs. output current, all I/Os excluding DP/DM, Vqc = 3V. Figure 32-4. Output low voltage vs. output current, all I/Os excluding DP/DM, Vqq = 5V. 406 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 32-5. Output high voltage vs. output current, all I/Os excluding DP/DM, Vqq = 3V. 0 5 10 15 20 loH (mA) — 85 25 ^•^-40 Figure 32-6. Output high voltage vs. output current, all I/Os excluding DP/DM, Vqc = 5V. ^iniEL 7593L-AVR-09/12 407 32.3 Power-down supply current Figure 32-8. Power-down supply current vs. Vqq, with BOD disabled, WDT enabled, T = 25°C. 408 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 32-9. Power-down supply current vs. Vqq, with BOD enabled, WDT enabled, T = 25°C. 32.4 Power-save supply current Figure 32-10. Power-save supply current vs. Vqq, with BOD & WDT disabled, T = 25°C. ^iniEL 7593L-AVR-09/12 409 32.5 Idle supply current Figure 32-11. Idle supply current vs. frequency, T = 25°C. 32.6 Active supply current Figure 32-12. Active supply current vs. frequency, T = 25°C. 410 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 32.7 Reset supply current Figure 32-13. Reset supply current vs. frequency. 32.8 I/O pull-up current Figure 32-14. I/O pull-up current vs. pin voltage, Vqq = 5V. ^iniEL 7593L-AVR-09/12 411 Figure 32-15. Reset pull-up current vs. pin voltage, Vqq = 5V. - 85 - 25 -40 32.9 Bandgap voltage Figure 32-16. Bandgap voltage vs. temperature. —^5.5 -^ 5.0 ^^ 4.5 — 4.0 ^<- 3.6 —^ 2.7 412 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 32.10 Internal ARef voltage Figure 32-17. Internal ARef reference voltage vs. temperature, Vqq = 2.7-5.5V. 32.11 USB regulator Figure 32-18. USB regulator quiescent current vs. input voltage, no load. 100 90 80 70 60 50 40 30 20 10 0 V ^ 3.0 3.5 4.0 4.5 Voltage (V) 5.0 5.5 6.0 ^rniEL e 7593L-AVR-09/12 413 Figure 32-19. USB regulator output voltage vs. input voltage, load = 75Q. hput Voltage (V) Note: The 75Q. load is equivalent to the maximum average consumption of the USB peripheral in opera- tion (fuli bus load). 32.12 BOD levels Figure 32-20. BOD voltage (2.4V level) vs. temperature. 414 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 32-21. BOD voltage (3.4V level) vs. temperature. Figure 32-22. BOD voltage (4.3V level) vs. temperature. ^iniEL 7593L-AVR-09/12 415 32.13 Watchdog timer frequency Figure 32-23. WDT oscillator frequency vs. Vqq. 32.14 Internal RC oscillator frequency Figure 32-24. RC oscillator frequency vs. OSCCAL, T = 25°C. 416 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Figure 32-25. RC oscillator frequency vs. Vqq. Figure 32-26. RC oscillator frequency vs. temperature. —^ 5.5 — 4.0 ^*^ 3.3 3.0 ^<- 2.7 ^iniEL 7593L-AVR-09/12 417 32.15 Power-on reset Figure 32-27. Power-on reset level vs. temperature. Temperature (°C) 418 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 33. Register summary Address Name Bit 7 Bite Bit 5 Bit 4 Bits Bits Bit1 BitO Page (OxFF) Reserved - (OxFE) Reserved - (OxFD) Reserved - (OxFC) Reserved - (OxFB) Reserved - (OxFA) Reserved - (0xF9) OTGTCON PAGE VALUE (0xF8) UPINT PINT7:0 (0xF7) UPBCHX I - I - I - I - I PBYCT10:8 (OxF6) UPBCLX PBYCT7:0 (0xF5) UPERRX COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL (0xF4) UEINT EPINT6;0 (0xF3) UEBCHX I - I - I - I BYCT10:8 (0xF2) UEBCLX BYCT7:0 (OxFI) UEDATX DAT7;0 (OxFO) UEIENX FLERRE NAKINE NAKOUTE RXSTPE RXOUTE STALLEDE TXINE (OxEF) UESTA1X - CTRLDIR CURRBK1:0 (OxEE) UESTAOX CFGOK OVERFI UNDERFI DTSEQ1;0 NBUSYBK1:0 (OxED) UECFG1X EPSiZE2;0 EPBK1:0 ALLOC (OxEC) UECFGOX EPTYPE1:0 - EPDIR (OxEB) UECONX STALLRQ STALLRQC RSTDT EPEN (OxEA) UERST EPRST6;0 (0xE9) UENUM EPNUM2:0 (OxES) UEINTX FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI (OxE7) Reserved (0xE6} UDMFN FNCERR (OxES) UDFNUMH FNUM10:8 {0xE4) UDFNUML FNUM7;0 (0xE3} UDADDR ADDEN UADD6:0 (0xE2) UDIEN UPRSME EORSME WAKEUPE EORSTE SOFE SUSPE (OxE1} UDINT UPRSMI EORSMI WAKEUPI EORSTI SOFI SUSPI (OxEO) UDCON LSM RMWKUP DETACH (OxDF) OTGINT STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI (OxDE) OTGIEN STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE (OxDD) OTGCON HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC (OxDC) Reserved (OxDB) Reserved (OxDA) USBINT IDTI VBUSTI (0xD9) USBSTA SPEED ID VBUS (0xD8) USBCON USBE HOST FRZCLK OTGPADE IDTE VBUSTE (OxD7) UHWCON UIMOD UIDE UVCONE UVREGE (0xD6) Reserved (OxDS) Reserved (OxD4) Reserved (0xD3) Reserved (OxD2) Reserved - {OxD1) Reserved - (OxDO) Reserved - (OxCF) Reserved - (OxCE) UDR1 USART1 I/O Data Register (OxCD) UBRR1H I - I - I - I USART1 Baud Rate Register High Byte (OxCC) UBRR1L USART1 Baud Rate Register Low Byte (OxCB) Reserved - - (OxCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 {0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 (OxCS) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 PEI U2X1 MPCM1 {OxC7) Reserved - (0xC6) Reserved - (OxCS) Reserved - (OxC4) Reserved - - (0xC3) Reserved - (OxC2) Reserved - - (OxC1) Reserved - - - - - - (OxCO) Reserved - - - - - - (OxBF) Reserved - - - - - 7593L-AVR-09/12 419 ^imEL Address Name Bit 7 Bite Bite Bit 4 Bits Bits Bit1 BitO Page (OxBE) Reserved - (OxBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAMO (OxBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE (OxBB) TWDR 2-wire Serial Interface Data Register (OxBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWAO TWGCE (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 TWPS1 TWPSO (0xB8) TWBR 2-wire Serial Interface Bit Rate Register (OxB7) Reserved - (0xB6} ASSR EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB (OxB5) Reserved - - (0xB4} 0CR2B Tirner/Counter2 Output Compare Register B (0xB3) 0CR2A Timer/Counter2 Output Compare Register A (0xB2) TCNT2 Timer/Counter2 (8 Bit) (OxB1) TCCR2B FOC2A FOC2B WGM22 CS22 CS21 CS20 (OxBO) TCCR2A COM2A1 COM2AO COM2B1 COM2BO WGM21 WGM20 (OxAF) U PD ATX PDAT7:0 (OxAE) UPIENX FLERRE I NAKEDE | - | PERRE | TXSTPE | TXOUTE | RXSTALLE | RXINE (OxAD) UPCFG2X INTFRQ7:0 (OxAC) UPSTAX CFGOK OVERFI 1 UNDERFI | DTSEQTO NBUSYBK1:0 (OxAB) UPCFG1X PSIZE2:0 PBK1:0 ALLOC I (OxAA) UPCFGOX PTYPE1:0 PTOKEN1:0 PEPNUM3:0 (0xA9) UPCONX PFREEZE INMODE I RSTDT 1 1 1 PEN (0xA8) UPRST PRST6:0 (OxA7) UPNUM PNUM2:0 (0xA6) UPINTX FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI 1 RXSTALLI | RXINI (0xA5) UPINRQX INRQ7:0 (OxA4) UHFLEN FLEN7:0 (0xA3} UHFNUMH I I I I I FNUM10:8 (0xA2} UHFNUML FNUM7;0 (OxA1) UHADDR HADD6:0 (OxAO) UHIEN HWUPE HSOFE RXRSME RSMEDE RSTE DDISCE DCONNE (0x9F) UHINT HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI (0x9E} UHCON RESUME RESET SOFEN (0x9D) OCR3CH Timer/CounterS - Output Compare Register C High Byte (0x9C) OCR3CL Timer/Counter3 - Output Compare Register C Low Byte (0x9B) OCR3BH Timer/Counter3 - Output Compare Register B High Byte (0x9A) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte (0x99) OCR3AH Timer/Counter3 - Output Compare Register A High Byte (0x98) OCR3AL Timer/CounterS - Output Compare Register A Low Byte (0x97) ICR3H Timer/CounterS - Input Capture Register High Byte (0x96) ICR3L Timer/CounterS - Input Capture Register Low Byte (0x95) TCNT3H Timer/CounterS - Counter Register High Byte (0x94) TCNT3L Timer/CounterS - Counter Register Low Byte (0x93) Reserved - - (0x92) TCCR3C FOC3A FOC3B FOC3C (0x91) TCCR3B ICNC3 ICES3 WGM33 WGM32 CS32 CS31 CS30 (0x90) TCCR3A COM3A1 COM3AO COM3B1 COM3BO COM3C1 COM3CO WGM31 WGM30 (0x8F) Reserved - - (0x8E) Reserved - - (0x8D) OCR1CH Timer/Counter1 - Output Compare Register C High Byte (0x8C) OCR1CL Timer/Counterl - Output Compare Register C Low Byte (0x8B) OCR1BH Timer/Counterl - Output Compare Register B High Byte (0x8A) OCR1BL Timer/Counterl - Output Compare Register B Low Byte (0x89) OCR1AH Timer/Counterl - Output Compare Register A High Byte (0x88) OCR1AL Timer/Counterl - Output Compare Register A Low Byte (0x87) ICR1H Timer/Counterl - Input Capture Register High Byte (0x86) ICR1L Timer/Counterl - Input Capture Register Low Byte (0x85) TCNT1 H Timer/Counterl - Counter Register High Byte (0x84) TCNT1L Timer/Counterl - Counter Register Low Byte (0x83) Reserved - (0x82) TCCR1C FOC1A FOC1B FOC1C (0x81) TCCR1B ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 (0x7F) DIDR1 - AIN1D AINOD (0x7E) DIDRO ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADCOD (Ox7D) - - - 420 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Address Name Bit 7 Bite Bits Bit 4 Bits Bits Bit1 BitO Page (Ox7C) ADMUX REFS1 REFSO ADLAR MUX4 MUX3 MUX2 MUX1 MUXO (Ox7B) ADCSRB ADHSM ACME ADTS2 ADTS1 ADTSO (Ox7A} ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO (0x79) ADCH ADC Data Register High byte (0x78) ADCL ADC Data Register Low byte (0x77) Reserved - (0x76) Reserved - (0x75) XMCRB XMBK - XMM2 XMM1 XMMO (0x74) XMCRA SRE SRL2 SRL1 SRLO SRW11 SRW10 SRW01 SR WOO (0x73) Reserved - - (0x72) Reserved - (0x71) TIMSK3 - ICIE3 OCIE3C OCIE3B OCIE3A TOIE3 (0x70) TIMSK2 - OCIE2B OCIE2A TOIE2 (0x6F) TIMSK1 - ICIE1 OCIE1C OCIE1B OCIE1A TOIE1 (0x6E) TIMSKO - OCIEOB OCIEOA TOIEO (0x6D) Reserved - (0x6C) Reserved - (0x6B) PCMSKO PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO (0x6A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 (0x69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISCOO (0x68) PCICR - PCIEO (0x67) Reserved - (0x66) OSCCAL Oscillator Calibration Register (0x65) PRR1 PRUSB - PRTIM3 PRUSART1 (0x64) PRRO PRTWI PRTIM2 PRTIMO PRTIM1 PRSPI PRADC (0x63) Reserved - (0x62) Reserved - (0x61) CLKPR CLKPCE - CLKPS3 CLKPS2 CLKPS1 CLKPSO (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDPO 0x3F (0x5F) SREG I T H S V N Z C 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SPI SPO 0x3C (0x5C} Reserved - 0x3B (0x5B) RAMPZ - RAMPZ1 RAMPZO 0x3A (0x5A) Reserved - - 0x39 (0x59) Reserved - 0x38 (0x58) Reserved - 0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 0x36 (0x56) Reserved - 0x35 (0x55) MCUCR JTD - PUD IVSEL IVCE 0x34 (0x54) MCUSR - JTRF WDRF BORF EXTRF PORF 0x33 (0x53) SMCR - SM2 SMI SMO SE 0x32 (0x52) Reserved - 0x31 (0x51) OCDR/ OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDRO MONDR Monitor Data Register 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACISO 0x2F (0x4F) Reserved - 0x2E (0x4E) SPDR SPI Data Register 0x2D (0x4D) SPSR SPIF WCOL SPI2X 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 0x29 (0x49) PLLCSR - - - PLLP2 PLLP1 PLLPO PILE PLOCK 0x28 (0x48) OCROB Timer/CounterO Output Compare Register B 0x27 (0x47) OCROA Timer/CounterO Output Compare Register A 0x26 (0x46) TCNTO Timer/CounterO (8 Bit) 0x25 (0x45) TCCROB FOCOA FOCOB WGM02 CS02 CS01 CSOO 0x24 (0x44) TCCROA COM0A1 COMOAO COMOB1 COMOBO WGM01 WGMOO 0x23 (0x43) GTCCR TSM - PSRASY PSRSYNC 0x22 (0x42) EEARH - EEPROM Address Register High Byte 0x21 (0x41) EEARL EEPROM Address Register Low Byte 0x20 (0x40) EEDR EEPROM Data Register 0x1F(0x3F) EECR - - EEPM1 EEPMO EERIE EEMPE EEPE EERE 0x1 E (0x3E) GPIORO General Purpose I/O Register 0 0x1 D (0x3D) EIMSK INT7 INT6 I NTS INT4 INT3 INT2 INTI INTO 0x1 C (0x3C} EIFR INTF7 INTF6 I NTFS INTF4 INTF3 INTF2 INTF1 INTFO 7593L-AVR-09/12 421 Address Name Bit 7 Bite Bite Bit 4 Bits Bits Biti BitO Page 0x1 B (0x3B) PCIFR - PCIFO 0x1A(0x3A) Reserved - 0x19 (0x39) Reserved - 0x18(0x38} TIFR3 - ICF3 OCF3C OCF3B OCF3A TOV3 0x17 (0x37) TIFR2 - OCF2B OCF2A TOV2 0x16(0x36) TIFR1 - ICF1 OCF1C OCF1B OCF1A TOV1 0x15(0x35) TIFRO - OCFOB OCFOA TOVO 0x14(0x34) Reserved - 0x13(0x33) Reserved - 0x12 (0x32) Reserved - 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTFO 0x10(0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO OxOF (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINFO OxOE (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTEO OxOD (0x2D} DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO OxOC (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINEO OxOB (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTDO OxOA (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTCO 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDCO 0x06 (0x26) PING PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINCO 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINBO 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTAO 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDAO 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINAO Note: 1 . For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg- isters, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1 F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The Atmel AT90USB64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 422 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 34. Instruction set summary Mnemonics Operands Description Operation Flags #Clocks ARITHME' nc AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd <- Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word RdhiRdl <- RdhiRdI + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ■(- Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd <- Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd<-Rd-Rr-C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd <- Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl^Rdh:Rdl-K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd <- Rd - K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd V Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ■(- Rd V K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd <- Rd @ Rr Z,N,V 1 COM Rd One’s Complement Rd ■(- OxFF - Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd <- 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd <- Rd V K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ■(- Rd • (OxFF - K) Z,N,V 1 INC Rd Increment Rd ^ Rd + 1 Z,N,V 1 DEC Rd Decrement Rd <- Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd <- Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd <— Rd @ Rd Z,N,V 1 SER Rd Set Register Rd ^ OxFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0<-RdxRr z,c 2 MULS Rd, Rr Multiply Signed R1:R0<-RdxRr z,c 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0<-RdxRr z,c 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0<-(RdxRr) « 1 z,c 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0^(RdxRr)« 1 z,c 2 FMULSU Rd, Rr Fractional Multiply Siqned with Unsiqned R1:R0^(RdxRr)« 1 z,c 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC + k +1 None 2 IJMP Indirect Jump to (Z) PC*-Z None 2 EIJMP Extended Indirect Jump to (Z) PC <-{EIND:Z) None 2 JMP k Direct Jump PC-(- k None 3 RCALL k Relative Subroutine Call PC ■(- PC + k + 1 None 4 ICALL Indirect Cali to (Z) PC<-Z None 4 EICALL Extended Indirect Call to (Z) PC <-(EIND:Z) None 4 CALL k Direct Subroutine Call PC^k None 5 RET Subroutine Return PC ^ STACK None 5 RETI Interrupt Return PC STACK I 5 CPSE Rd,Rr Compare, Skip if Equal if(Rd = Rr) PC ■(- PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd-Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd-Rr-C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd-K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0} PC ■(- PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1)PC-(-PC + 2or3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC <- PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if{P(b)=1)PC<-PC + 2or3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1 ) then PC<-PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC<-PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z=1}then PC <- PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1)then PC<-PC + k+1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC <- PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC <- PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1)then PC<-PC + k+1 None 1/2 BRMI k Branch if Minus if(N = 1)then PC^PC + k+1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC <- PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N © V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N © V= 1 ) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if(H = 1)then PC<-PC + k+1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC <- PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if{T=1)thenPC<-PC + k +1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0} then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1)then PC<-PC + k + 1 None 1/2 7593L-AVR-09/12 423 ^imEL Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flaa is Cleared if fV = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (1 = 1) then PC<-PC + k+1 None 1/2 BRID k Branch if Interrupt Disabled if ( 1 = 0) then PC •«- PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P.b Set Bit in I/O Register l/0(P,b) ■(- 1 None 2 CBI P,b Clear Bit in I/O Register l/0(P,b) ^ 0 None 2 LSL Rd Logical Shift Left Rd(n+1)<-Rd(n), Rd(0}<-0 Z.C.N.V 1 LSR Rd Logical Shift Right Rd(n)-(-Rd(n+1), Rd{7)<-0 Z.C.N.V 1 ROL Rd Rotate Left Through Carry Rd(0)<-C,Rd{n+1)^ Rd(n),C-«-Rd(7) Z.C.N.V 1 ROR Rd Rotate Right Through Carry Rd{7)<-C,Rd{n)<- Rd(n+1),C<-Rd(0) Z.C.N.V 1 ASR Rd Arithmetic Shift Right Rd(n) ^ Rd(n+1), n=0..6 Z.C.N.V 1 SWAP Rd Swap Nibbles Rd(3..0)<-Rd{7..4),Rd(7..4}-(-Rd(3..0) None 1 BSET s Flag Set SREG(s)^1 SREG(s) 1 BCLR s Flag Clear SREG(s) ■(- 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T <- Rr(b) T 1 BLD Rd. b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C<-1 C 1 CLC Clear Carry C<-0 C 1 SEN Set Negative Flag N <- 1 N 1 CLN Clear Negative Flag N<-0 N 1 SEZ Set Zero Flag Z<- 1 Z 1 CLZ Clear Zero Flag Z^O Z 1 SEI Global Interrupt Enable 1 <- 1 1 1 CLI Global Interrupt Disable l<-0 1 1 SES Set Signed Test Flag S<- 1 S 1 CLS Clear Signed Test Flag S<-0 S 1 SEV Set Twos Complement Overflow. V-(- 1 V 1 CLV Clear Twos Complement Overflow V-(-0 V 1 SET Set T in SREG T<- 1 T 1 CLT Clear T in SREG T<-0 T 1 SEH Set Half Carry Flag in SREG H-(-1 H 1 CLH Clear Half Carry Flag in SREG H-t-0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd<-Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd <- K None 1 LD Rd,X Load Indirect Rd (X) None 2 LD Rd. X+ Load Indirect and Post-Inc. Rd (X), X <- X + 1 None 2 LD Rd, -X Load Indirect and Pre-Dec. X X - 1 , Rd (X) None 2 LD Rd, Y Load Indirect Rd <- (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd <- (Y), Y <- Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-Dec. Y <- Y - 1 , Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd <- (Y + q) None 2 LD Rd, Z Load Indirect Rd ^ (Z) None 2 LD Rd. Z+ Load Indirect and Post-Inc. Rd<-(Z),Z<-Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z <- Z - 1 , Rd ^ (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ■(- (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ^(k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST -X, Rr Store Indirect and Pre-Dec. X <- X - 1 . (X) <- Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y <- Y - 1 , (Y) <- Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) <- Rr None 2 ST Z, Rr Store Indirect (Z) ^ Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) <- Rr. Z <- Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z <- Z - 1 , (Z) ■(- Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q)^Rr None 2 STS k, Rr Store Direct to SRAM (k) ^ Rr None 2 LPM Load Program Memory RO^(Z) None 3 LPM Rd, Z Load Program Memory Rd ^ (Z) None 3 LPM Rd. Z+ Load Program Memory and Post-Inc Rd<-(Z),Z<-Z+1 None 3 ELPM Extended Load Program Memory RO (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd ^ (Z) None 3 ELPM Rd, Z+ Extended Load Program Memory Rd ■«- (RAMPZiZ), RAMPZ:Z <-RAMPZ:Z+1 None 3 424 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Mnemonics Operands Description Operation Fiags #Ciocks SPM Store Program Memory (Z) R1:R0 None - IN Rd, P In Port Rd<-P None 1 OUT P, Rr Out Port P <- Rr None 1 PUSH Rr Push Reoister on Stack STACK ^ Rr None 2 POP Rd Poo Register from Stack Rd <- STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A ^iniEL 7593L-AVR-09/12 425 35. Ordering information 35.1 Atmel AT90USB646 Speed [MHz] Power supply [V] Ordering code USB interface Package Operating range 16(3) 2.7-5.5 AT90USB646-AU Device MD Industrial AT90USB646-MU PS (-40° to +85°C) Notes: 1 . This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully green. 3. See “Maximum speed vs. VCC” on page 392. MD 64 - lead, 14x1 4mm body size, 1 .0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) PS 64 - lead, 9 x 9mm body size, 0.50mm pitch Quad flat no lead package (QFN) 426 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 35.2 Atmel AT90USB647 Speed [MHz] Power supply [V] Ordering code USB interface Package Operating range 16(3) 2.7-5.5 AT90USB647-AU USB OTG MD Industrial AT90USB647-MU PS (-40° to -i-85°C) Notes: 1 . This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully green. 3. See “Maximum speed vs. VCC” on page 392. MD 64 - lead, 14x1 4mm body size, 1 .0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) PS 64 - lead, 9 x 9mm body size, 0.50mm pitch Quad flat no lead package (QFN) ^iniEL 7593L-AVR-09/12 427 35.3 Atmel AT90USB1286 Speed [MHz] Power supply [V] Ordering code USB interface Package Operating range 16(3) 2.7-5.5 AT90USB1286-AU Device MD Industrial AT90USB1 286-MU PS (-40° to -i-85°C) Notes: 1 . This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully green. 3. See “Maximum speed vs. VCC” on page 392. MD 64 - lead, 14x1 4mm body size, 1 .0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) PS 64 - lead, 9 x 9mm body size, 0.50mm pitch Quad flat no lead package (QFN) 428 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 35.4 Atmel AT90USB1287 Speed [MHz] Power supply [V] Ordering code USB interface Package Operating range 16(3) 2.7-5.5 AT90USB1287-AU Host (OTG) MD Industrial AT90USB1 287-MU PS (-40° to -i-85°C) Notes: 1 . This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully green. 3. See “Maximum speed vs. VCC” on page 392. MD 64 - lead, 14x1 4mm body size, 1 .0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) PS 64 - lead, 9 x 9mm body size, 0.50mm pitch Quad flat no lead package (QFN) ^iniEL 7593L-AVR-09/12 429 36. Packaging information 36.1 TQFP64 A . L n* tn r : £. COMMON DiMENSIONS IN MM SYMBOL M i n Max NOTES A — 1. 20 A1 0. 95 1. 05 C 0. 09 0. 20 D 16. 00 BSC D1 14. 00 BSC E 16. 00 BSC El 14, 00 BSC J 0. 05 0. 15 L 0. 45 0. 75 e 0. 80 BSC f 0. 30 0. 45 07/26/07 Atmel Nantes S.A. La Chantrerie - BP 70602 44306 Nantes Cedex 3 - France TITLE MD, 64 - Lead, 14x14 mm Body Size, 1 .0 mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING No. MD REV. F 430 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 NOTES: STANDARD NOTES EOR PQEP/VQEP/TQEP/DQEP 1. DIMENSIONING & TOLERANCING GONFORM TO ASME Y14.5M. - 1982. 2. ”D1 AND El” DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH) . THE TOP PAOKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PAOKAGE BODY SIZE BY AS MUOH AS 0.15 mm. 3. DATUM PLANE ”H” LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXISTS PLASTIC BODY AT BOTTOM OF PARTING LINE. 4. DATUM ”A” AND ”D” TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSION ”f” DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm/.003” TOTAL EXOESS OF THE ”f” DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. ^iniEL « 7593L-AVR-09/12 431 36.2 QFN64 TOP VIEW DRAWINGS NDT SCALED A SIDE VIEW CDMMDN DIMENSIONS IN MM SYMBOL MIN, NDM, MAX, NOTES A 0. 80 — 1. 00 J 0. 00 — 0. 05 D/E 9. 00 BSC D2/E2 7. 40 7, 50 7. 60 N 64 e 0. 50 BSC L 0. 30 0, 40 0. 55 b 0. 18 0, 85 0. 30 □otion A □ption B CC 0. 30) (0. 20 R) Option C Tr i ang le Conp [ i ani; JEDEC Standard MD-220 var i at i on VMMD-3 28/11/08 TITLE DRAWING No. REV. Atmel Nantes S.A. La Chantrerie - BP 70602 PS, 64 - Lead 9. 0x9.0 mm Body, 0.50 mm Pitch PS K 44306 Nantes Cedex 3 - France Quad Flat No Lead Package (QFN) 432 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 NOTES: QFN STANDARD NOTES 1. DIMENSIONING Sc TOLERANCING GONFORM TO ASME Y14.5M. - 1994. 2. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 3. MAX. PACKAGE WARPAGE IS 0.05mm. 4. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 5. PIN #1 ID ON TOP WILL BE LASER MARKED. 6. THIS DRAWING CONFORMES TO JEDEC REGISTERED OUTLINE MO-220. 7. A MAXIMUM 0.15mm PULL BACK (LI) MAY BE PRESENT. L MINUS LI TO BE EQUAL TO OR GREATER THAN 0.30 mm 8. THE TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER BE EITHER A MOLD OR MARKED FEATURE 7593L-AVR-09/12 433 37. Errata 37.1 Atmel AT90USB1 287/6 errata 37.1 .1 AT90USB1 287/6 errata history Silicon Release 90USB1 286-1 6MU 90USB1 287-1 6AU 90USB1 287-1 6MU First Release Date Code up to 0648 Date Code up to 0714 and lots 0735 6H2726 Date Code up to 0701 Second Release Date Code from 0709 to 0801 except lots 0801 7H5103 from Date Code 0722 to 0806 except lots 0735 6H2726 Date Code from 0714 to 0810 except lots 0748 7H5103 h* Third Release Lots 0801 7H5103 and Date Code from 0814 Date Code from 0814 Lots 0748 7H5103 and Date Code from 0814 Fourth Release TBD TBD TBD Notes: 1 . A blank or any alphanumeric string. 37.1 .2 AT90USB1 287/6 first reiease • Incorrect CPU behavior for VBUSTI and IDTI interrupts routines • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • VBUS Session valid threshold voltage • USB signal rate • VBUS residual level • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 9. incorrect CPU behavior for VBUSTi and iDTi interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 8. USB Eye Diagram vioiation in iow-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 7. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does 434 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical SOOpA extra-power con- sumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 6. VBUS session valid threshold voltage The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.). That causes the device to attach to the bus only when Vbus is greater than VBusValid instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached. Problem fix/workaround According to the USB power drop budget, this may require connecting the device toa root hub or a self-powered hub. 5. UBS signal rate The average USB signal rate may sometime be measured out of the USB specifications (12MHz ±30kHz) with short frames. When measured on a long period, the average signal rate value complies with the specifications. This bit rate deviation does not generates com- munication or functional errors. Problem fix/workaround None. 4. VBUS residual level In USB device and host mode, once a 5V level has been detected to the VBUS pad, a resid- ual level (about 3V) can be measured on the VBUS pin. Problem fix/workaround None. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem tix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 7593L-AVR-09/12 435 1 . Asynchronous timer interrupt wake up from sieep generates muitipie interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep again it may wake up multipie times. Problem fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2+1 . AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 37.1 .3 Atmel AT90USB1 287/6 second release • Incorrect CPU behavior for VBUSTI and IDTI interrupts routines • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • VBUS Session valid threshoid voltage • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 7. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 6. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 5. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB iines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300pA extra-power con- sumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 4. VBUS session valid threshold voltage The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.). That causes the device to attach to the bus only when Vbus is greater than VBusValid instead of V_Session Vaiid. Thus if VBUS is lower than 4.4V, the device is detached. Problem fix/workaround According to the USB power drop budget, this may require connecting the device toa root hub or a self-powered hub. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI is enabled. 7593L-AVR-09/12 437 Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1 . Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep again it may wake up multipie times. Problem fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2 -h1 . 438 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 37.1 .4 Atmel AT90USB1 287/6 Third Release • Incorrect CPU behavior for VBUSTI and IDTI interrupts routines • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 5. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines The CPU core may incorrectly execute the interrupt vector reiated to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit. The internal USB engine remains in suspend mode but the USB differ- ential receiver is still enabled and generates a typical 300pA extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by soft- ware (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem fix/workaround No known workaround, enable AT90USB64/128 TWI first, before the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from sleep mode should be disabled. 1 . Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and then goes back into sleep mode, it may wake up multiple times. 7593L-AVR-09/12 439 Problem fix/workaround A software workaround is to wait before performing the sleep instruction: until TCNT2>OCR2+1 . AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 37.1 .5 Atmel AT90USB1 287/6 Fourth Release • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit. The internal USB engine remains in suspend mode but the USB differ- ential receiver is still enabled and generates a typical 300pA extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by soft- ware (Instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI Is enabled. Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first, before the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from sleep mode should be disabled. 1 . Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and then goes back into sleep mode, it may wake up multiple times. Problem fix/workaround A software workaround is to wait before performing the sleep Instruction: until TCNT2>OCR2 -h1 . 7593L-AVR-09/12 441 37.2 Atmel AT90USB646/7 errata 37.2.1 AT90USB646/7 errata history TBD Silicon Release 90USB646-16MU 90USB647-16AU 90USB647-16MU First Release Second Release Note means a blank or any alphanumeric string. 37.2.2 AT90USB646/7 first reiease. • Incorrect interrupt routine execution for VBUSTI, IDTI interrupts flags • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 6. incorrect CPU behavior for VBUSTi and iDTi interrupts routines The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI interrupt flags. Problem fix/workaround Do not enable these interrupts, firmware must process these USB events by polling VBUSTI and IDTI flags. 5. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300pA extra-power con- sumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI is enabled. 442 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1 . Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep mode again it may wake up several times. Problem fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2 -h1 . ^iniEL 7593L-AVR-09/12 443 37.2.3 Atmel AT90USB646/7 Second Release. • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 5. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state. However the idle state following the perturbation does not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300pA extra-power con- sumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 3. Spike on TWI pins when TWI is enabled 100ns negative spike occurs on SDA and SCL pins when TWI is enabled. Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1 . Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep mode again it may wake up several times. Problem fix/workaround A software workaround is to wait with performing the sleep instruction until TCNT2>OCR2 -h1 . 444 AT90USB64/128 7593L-AVR-09/12 AT90USB64/128 38. Datasheet revision history for Atmei AT90USB64/1 28 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 38.1 Changes from 7593A to 7593B 1 . Changed defauit configuration for fuse bytes and security byte. 2. Suppression of timer 4,5 registers which does not exist. 3. Updated typical application schematics in USB section 38.2 Changes from 7593B to 7593C 1 . Update to package drawings, MQFP64 and TQFP64. 38.3 Changes from 7593C to 7593D 1 . For further product compatibiiity, changed USB PLL possible prescaler configurations. Only 8MHz and 16MHz crystal frequencies allows USB operation (see Table 7-1 1 on page 50). 38.4 Changes from 7593D to 7593E 1 . Updated PLL Prescaler table: configuration words are different between AT90USB64x and AT90USB128X to enable the PLL with a 16MHz source. 2. Cleaned up some bits from USB registers, and updated information about OTG timers, remote wake-up, reset and connection timings. 3. Updated clock distribution tree diagram (USB prescaler source and configuration register). 4. Cleaned up register summary. 5. Suppressed PCINT23:8 that do not exist from External Interrupts. 6. Updated Electrical Characteristics. 7. Added Typical Characteristics. 8. Update Errata section. 38.5 Changes from 7593E to 7593F 1 . Removed ’Preliminary’ from document status. 2. Clarification in Stand by mode regarding USB. 38.6 Changes from 7593F to 7593G 1 . Updated Errata section. 38.7 Changes from 7593G to 7593H 1 . Added Signature information for 64K devices. 2. Fixed figure for typical bus powered application 3. Added min/max values for BOD levels 4. Added ATmega32U6 product 5. Update Errata section 6. Modified descriptions for HWUPE and WAKEUPE interrupts enable (these interrupts should be enabled only to wake up the CPU core from power down mode). ^iniEL « 7593L-AVR-09/12 445 7. Added description to access unique serial number located in Signature Row see “Reading the Signature Row from software” on page 354. 38.8 Changes from 7593H to 75931 1 . Updated Table 9-2 in “Brown-out detection” on page 60. Unused BOD levels removed. 38.9 Changes from 75931 to 7593J 1 . Updated Table 9-2 in “Brown-out detection” on page 60. BOD level 100 removed. 2. Updated “Ordering information” on page 426. 3. Removed ATmega32U6 errata section. 38.10 Changes from 7593J to 7593K 1 . Corrected Figure 6-7 on page 34, Figure 6-8 on page 34 and Figure 6-9 on page 35. 2. Corrected ordering information for Section 35.3 "Atmel AT90USB1286” on page 428, Section 35.4 ’’Atmel AT90USB1287” on page 429 andSection 35.2 ’’Atmel AT90USB647” on page 427. 3. Removed the ATmega32U6 device and updated the datasheet accordingly. 4. Updated Assembly Code Example in “Watchdog reset” on page 61 . 38.1 1 Changes from 7593K to 7593L 1 . Updated the “Ordering information” on page 426. Changed the speed from 20MHz to 16MHz. 2. Replaced ATmegaAT90USBxxxx by AT90USBxxxx through the datasheet. 3. Updated the first paragraph of “Overview” on page 307. Port A replaced by Port F. 4. Updated ADC equation in “ADC conversion result” on page 318. The equation has 1024 instead of 1023. 5. Created “Packaging Information” chapter. 6. Replaced the “OFN64” Packaging by an updated OFN64 Packaging drawing. 7. Updated “Errata” on page 434. AT90USB1 286/7 has a fourth release, while AT90USB646/7 updated with a second release. 8. In Section “Overview” on page 307, “Port A” has been replaced by “Port F” in the first section. 9. In Section “Atmel AT90USB647” on page 427 the USB interface has been changed to USB OTG. 10. In Section “Atmel AT90USB1286” on page 428 the USB interface has been changed to Device. 1 1 . In Section “Atmel AT90USB1287” on page 429 the USB interface has been changed to Host OTG. 12. General update according to new template. 446 AT90USB64/128 7593L-AVR-09/12 AT90USB64X/128X Table of contents Features 1 1 Pin configurations 3 2 Overview 5 2.1 Block diagram 6 2.2 Pin descriptions 8 3 Resources 10 4 About code exam pies 10 5 AVR CPU core 11 5.1 Introduction 11 5.2 Architectural overview 1 1 5.3 ALU - Arithmetic Logic Unit 12 5.4 Status register 13 5.5 General purpose register file 14 5.6 Stack pointer 15 5.7 Instruction execution timing 16 5.8 Reset and interrupt handling 17 6 Atmei AVR A T90USB64/128 memories 20 6.1 In-system re-programmable flash program memory 20 6.2 SRAM data memory 21 6.3 EEPROM data memory 24 6.4 I/O memory 30 6.5 External memory interface 31 7 System dock and dock options 40 7.1 Clock systems and their distribution 40 7.2 Clock sources 41 7.3 Low power crystal oscillator 42 7.4 Low frequency crystal oscillator 44 7.5 Calibrated internal RC oscillator 45 7.6 External clock 46 7.7 Clock output buffer 47 7.8 Timer/counter oscillator 47 7.9 System clock prescaler 47 7593L-AVR-09/12 7.10 PLL 49 8 Power management and sleep modes 51 8.1 Idle mode 52 8.2 ADC noise reduction mode 52 8.3 Power-down mode 52 8.4 Power-save mode 52 8.5 Standby mode 53 8.6 Extended Standby mode 53 8.7 Power Reduction Register 54 8.8 Minimizing power consumption 55 9 System control and reset 57 9.1 Resetting the AVR 57 9.2 Reset sources 57 9.3 Power-on reset 58 9.4 External reset 59 9.5 Brown-out detection 60 9.6 Watchdog reset 61 9.7 Internal voltage reference 62 9.8 Watchdog timer 63 10 Interrupts 68 10.1 Interrupt vectors in AT90USB64/128 68 1 1 l/O-ports 71 11.1 Introduction 71 1 1 .2 Ports as general digital I/O 72 11.3 Alternate port functions 76 1 1 .4 Register description for l/O-ports 89 12 External Interrupts 92 13 TImer/CounterO, TImer/Counterl , and Tlmer/Counter3 prescalers ... 96 13.1 Internal clock source 96 13.2 Prescaler reset 96 13.3 External clock source 96 13.4 GTCCR - General Timer/Counter Control Register 97 14 8-blt TImer/CounterO with PWM 98 14.1 Overview 98 AT90USB64X/128X 7593L-AVR-09/12 AT90USB64X/128X 14.2 Timer/Counter clock sources 99 14.3 Counter unit 99 14.4 Output compare unit 100 14.5 Compare Match Output Unit 102 14.6 Modes of operation 103 14.7 Timer/Counter timing diagrams 107 14.8 8-bit Timer/Counter register description 108 15 16-bit Timer/Counter (Timer/Counterl and Timer/Counter3) 1 15 15.1 Overview 115 15.2 Accessing 16-bit registers 117 15.3 Timer/Counter clock sources 120 15.4 Counter unit 121 15.5 Input Capture unit 122 15.6 Output Compare units 124 15.7 Compare Match Output unit 126 1 5.8 Modes of operation 127 15.9 Timer/Counter timing diagrams 134 15.10 16-bit Timer/Counter register description 136 16 8-bit Timer/Counter2 with PWM and asynchronous operation 145 16.1 Overview 145 1 6.2 Timer/Counter clock sources 146 16.3 Counter unit 146 16.4 Output Compare unit 147 16.5 Compare Match Output unit 149 1 6.6 Modes of operation 150 16.7 Timer/Counter timing diagrams 154 1 6.8 8-bit Timer/Counter register description 156 1 6.9 Asynchronous operation of the Timer/Counter 161 16.10 Timer/Counter prescaler 164 17 Output Compare Modulator (OCM1C0A) 166 17.1 Overview 166 17.2 Description 166 18 SPI - Seriai Peripheral Interface 168 18.1 SS Pin Functionality 172 18.2 Data modes 175 19 USART 177 19.1 Overview 177 19.2 Clock generation 178 19.3 Frame formats 180 19.4 USART initialization 181 1 9.5 Data transmission - The USART transmitter 182 19.6 Data reception - The USART receiver 185 19.7 Asynchronous data reception 189 19.8 Multi-processor Communication mode 192 19.9 USART register description 193 19.10 Examples of baud rate setting 198 20 USART in SPI mode 202 20.1 Overview 202 20.2 Clock generation 202 20.3 SPI data modes and timing 203 20.4 Frame formats 203 20.5 Data transfer 205 20.6 USART MSPIM register description 207 20.7 AVR USART MSPIM vs. AVR SPI 209 21 2-wire serial interface 211 21.1 Features 211 21.2 2-wire Serial Interface bus definition 21 1 21.3 Data transfer and frame format 212 21 .4 Multi-master bus systems, arbitration and synchronization 215 21.5 Overview of the TWI module 216 21.6 TWI register description 219 21.7 Using the TWI 222 21.8 Transmission modes 225 21 .9 Multi-master systems and arbitration 239 22 USB controller 241 22.1 Features 241 22.2 Block diagram 241 22.3 Typical application implementation 242 22.4 General operating modes 246 22.5 Power modes 250 IV AT90USB64X/128X 7593L-AVR-09/12 AT90USB64X/128X 22.6 Speed control 251 22.7 Memory management 252 22.8 PAD suspend 253 22.9 OTG timers customizing 254 22.10 Plug-in detection 255 22.11 ID detection 256 22.12 Registers description 256 22.13 USB Software Operating modes 261 23 USB device operating modes 262 23.1 Introduction 262 23.2 Power-on and reset 262 23.3 Endpoint reset 262 23.4 USB reset 263 23.5 Endpoint selection 263 23.6 Endpoint activation 263 23.7 Address setup 264 23.8 Suspend, wake-up and resume 265 23.9 Detach 265 23.10 Remote Wake-up 266 23.11 STALL request 266 23.12 CONTROL endpoint management 267 23.13 OUT endpoint management 268 23.14 IN endpoint management 269 23.15 Isochronous mode 271 23.16 Overflow 272 23.17 Interrupts 272 23.18 Registers 273 24 USB host operating modes 285 24.1 Pipe description 285 24.2 Detach 285 24.3 Power-on and reset 285 24.4 Device detection 286 24.5 Pipe selection 286 24.6 Pipe configuration 286 24.7 USB reset 288 « V 7593L-AVR-09/12 24.8 Address setup 288 24.9 Remote wake-up detection 288 24.10 USB pipe reset 288 24. 11 Pipe data access 288 24.12 Control pipe management 289 24.13 OUT pipe management 289 24.14 IN Pipe management 290 24.15 Interrupt system 291 24.16 Registers 292 25 Analog Comparator 304 25.1 Analog Comparator multipiexed input 306 26 ADC - Analog to Digital Converter 307 26.1 Features 307 26.2 Overview 307 26.3 Operation 309 26.4 Starting a conversion 309 26.5 Prescaling and conversion timing 310 26.6 Changing channel or reference selection 313 26.7 ADC noise canceler 314 26.8 ADC conversion result 318 26.9 ADC register description 321 27 JTAG interface and on-chip debug system 327 27.1 Overview 327 27.2 TAP - Test Access Port 327 27.3 TAP Controller 329 27.4 Using the Boundary-scan chain 330 27.5 Using the on-chip debug system 330 27.6 On-chip debug specific JTAG instructions 331 27.7 On-chip Debug related Register in I/O memory 332 27.8 Using the JTAG programming capabilities 332 27.9 Bibliography 332 28 IEEE 1149.1 (JTAG) boundary-scan 333 28.1 Features 333 28.2 System overview 333 28.3 Data registers 333 AT90USB64X/128X 7593L-AVR-09/12 AT90USB64X/128X 28.4 Boundary-scan specific JTAG instructions 335 28.5 Boundary-scan Related Register in I/O memory 336 28.6 Boundary-scan chain 337 28.7 Atmel AT90USB64/128 Boundary-scan order 340 28.8 Boundary-scan description language files 342 29 Boot Loader support - read-while-write self-programming 343 29.1 Boot Loader features 343 29.2 Application and Boot Loader flash sections 343 29.3 Read-while-write and no read-while-write flash sections 343 29.4 Boot Loader lock bits 346 29.5 Entering the Boot Loader program 347 29.6 Addressing the flash during self-programming 350 29.7 Self-programming the flash 351 30 Memory programming 359 30.1 Program and data memory lock bits 359 30.2 Fuse bits 360 30.3 Signature bytes 362 30.4 Calibration byte 362 30.5 Parallel programming parameters, pin mapping, and commands 362 30.6 Parallel programming 365 30.7 Serial downloading 373 30.8 Serial programming pin mapping 374 30.9 Programming via the JTAG interface 377 3 1 Electrical characteristics for Atmel A T90USB64/128 390 31.1 Absolute maximum ratings* 390 31.2 DC characteristics 390 31.3 External clock drive waveforms 392 31.4 External clock drive 392 31 .5 Maximum speed vs. Vqq 392 31.6 2-wire serial interface characteristics 393 31.7 SPI timing characteristics 395 31 .8 Hardware boot entrance timing characteristics 396 31.9 ADC characteristics 397 31.10 External data memory timing 399 32 Atmel AT90USB64/1 28 typical characteristics 404 32.1 Input voltage levels 405 32.2 Output voltage levels 406 32.3 Power-down supply current 408 32.4 Power-save supply current 409 32.5 Idle supply current 410 32.6 Active supply current 410 32.7 Reset supply current 411 32.8 I/O pull-up current 41 1 32.9 Bandgap voltage 412 32.10 Internal ARef voltage 413 32.11 USB regulator 413 32.12 BOD levels 414 32.13 Watchdog timer frequency 416 32.14 Internal RC oscillator frequency 416 32.15 Power-on reset 418 33 Register summary 419 34 Instruction set summary 423 35 Ordering information 426 35.1 Atmel AT90USB646 426 35.2 Atmel AT90USB647 427 35.3 Atmel AT90USB1 286 428 35.4 Atmel AT90USB1 287 429 36 Packaging information 430 36.1 TQFP64 430 36.2 OFN64 432 37 Errata 434 37.1 Atmel AT90USB1 287/6 errata 434 37.2 Atmel AT90USB646/7 errata 442 38 Datasheet revision history for Atmei A T90USB64/128 445 38.1 Changes from 7593A to 7593B 445 38.2 Changes from 7593B to 7593C 445 38.3 Changes from 7593C to 7593D 445 38.4 Changes from 7593D to 7593E 445 38.5 Changes from 7593E to 7593F 445 AT90USB64X/128X 7593L-AVR-09/12 AT90USB64X/128X 38.6 Changes from 7593F to 7593G 445 38.7 Changes from 7593G to 7593H 445 38.8 Changes from 7593H to 7593I 446 38.9 Changes from 7593I to 7593J 446 38.10 Changes from 7593J to 7593K 446 38.11 Changes from 7593K to 7593L 446 Table of contents / ^iniEL 7593L-AVR-09/12 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: {+1){408) 441-0311 Fax: (-i-1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: {-h852) 2245-6100 Fax: (-1-852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (-H49) 89-31970-0 Fax: {-h49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg 1-6-4 Osaki Shinagawa-ku Tokyo 104-0032 JAPAN Tel: (-1-81)3-6417-0300 Fax: (-H81) 3-6417-0370 © 2012 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio®, and others are registered trademarks or trademarks of Atmel Cor- poration or its subsidiaries. Windows® is a registered trademark of Microsoft Corporation in U.S. and or other countries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmei products. No iicense, express or impiied, by estoppei or otherwise, to any inteilectuai property right is granted by this document or in connection with the saie of Atmei products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROF- ITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or com- pieteness of the contents ot this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmei does not make any commitment to update the intormation contained herein. Unless specitically provided otherwise, Atmel products are not suit- able for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted tor use as components in applica- tions intended to support or sustain lite. 7593L-AVR-09/12