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00016 #ifndef _USB_DRV_H_
00017 #define _USB_DRV_H_
00018
00019
00020
00021
00022 typedef enum endpoint_parameter{ep_num, ep_type, ep_direction, ep_size, ep_bank, nyet_status} t_endpoint_parameter;
00023
00027
00028
00029
00030 #define MAX_EP_NB 7
00031
00032 #define EP_CONTROL 0
00033 #define EP_1 1
00034 #define EP_2 2
00035 #define EP_3 3
00036 #define EP_4 4
00037 #define EP_5 5
00038 #define EP_6 6
00039 #define EP_7 7
00040
00041 #define PIPE_CONTROL 0
00042 #define PIPE_0 0
00043 #define PIPE_1 1
00044 #define PIPE_2 2
00045 #define PIPE_3 3
00046 #define PIPE_4 4
00047 #define PIPE_5 5
00048 #define PIPE_6 6
00049 #define PIPE_7 7
00050
00051
00052 #define MSK_EP_DIR 0x7F
00053 #define MSK_UADD 0x7F
00054 #define MSK_EPTYPE 0xC0
00055 #define MSK_EPSIZE 0x70
00056 #define MSK_EPBK 0x0C
00057 #define MSK_DTSEQ 0x0C
00058 #define MSK_NBUSYBK 0x03
00059 #define MSK_CURRBK 0x03
00060 #define MSK_DAT 0xFF // UEDATX
00061 #define MSK_BYCTH 0x07 // UEBCHX
00062 #define MSK_BYCTL 0xFF // UEBCLX
00063 #define MSK_EPINT 0x7F // UEINT
00064 #define MSK_HADDR 0xFF // UHADDR
00065
00066
00067 #define MSK_PNUM 0x07 // UPNUM
00068 #define MSK_PRST 0x7F // UPRST
00069 #define MSK_PTYPE 0xC0 // UPCFG0X
00070 #define MSK_PTOKEN 0x30
00071 #define MSK_PEPNUM 0x0F
00072 #define MSK_PSIZE 0x70 // UPCFG1X
00073 #define MSK_PBK 0x0C
00074
00075 #define MSK_NBUSYBK 0x03
00076
00077 #define MSK_ERROR 0x1F
00078
00079 #define MSK_PTYPE 0xC0 // UPCFG0X
00080 #define MSK_PTOKEN 0x30
00081 #define MSK_TOKEN_SETUP 0x30
00082 #define MSK_TOKEN_IN 0x10
00083 #define MSK_TOKEN_OUT 0x20
00084 #define MSK_PEPNUM 0x0F
00085
00086 #define MSK_PSIZE 0x70 // UPCFG1X
00087 #define MSK_PBK 0x0C
00088
00089
00090
00091
00092 #define TYPE_CONTROL 0
00093 #define TYPE_ISOCHRONOUS 1
00094 #define TYPE_BULK 2
00095 #define TYPE_INTERRUPT 3
00096
00097
00098 #define DIRECTION_OUT 0
00099 #define DIRECTION_IN 1
00100
00101
00102 #define SIZE_8 0
00103 #define SIZE_16 1
00104 #define SIZE_32 2
00105 #define SIZE_64 3
00106 #define SIZE_128 4
00107 #define SIZE_256 5
00108 #define SIZE_512 6
00109 #define SIZE_1024 7
00110
00111
00112
00113 #define ONE_BANK 0
00114 #define TWO_BANKS 1
00115
00116
00117 #define NYET_ENABLED 0
00118 #define NYET_DISABLED 1
00119
00120
00121 #define TOKEN_SETUP 0
00122 #define TOKEN_IN 1
00123 #define TOKEN_OUT 2
00124
00125 #define Is_ep_addr_in(x) ( (x&0x80)? TRUE : FALSE)
00126
00127
00129 #define VBUSRISE_20MS 0x00 // HOST : Minimum delay after Vbus requested to get it > Va_vbus_valid (otherwise => error)
00130 #define VBUSRISE_50MS 0x01
00131 #define VBUSRISE_70MS 0x02
00132 #define VBUSRISE_100MS 0x03
00133
00134 #define VBUSPULSE_15MS 0x20 // DEVICE : Duration of Vbus pulse during SRP protocol
00135 #define VBUSPULSE_23MS 0x21
00136 #define VBUSPULSE_31MS 0x22
00137 #define VBUSPULSE_40MS 0x23
00138
00139 #define VFALLTMOUT_93MS 0x40 // DEVICE : Minimum delay after Vbus < Vb_sess_end to enable SRP
00140 #define VFALLTMOUT_105MS 0x41
00141 #define VFALLTMOUT_118MS 0x42
00142 #define VFALLTMOUT_131MS 0x43
00143
00144 #define SRPMINDET_10US 0x60 // HOST : Minimum pulse duration accepted as SRP pulse
00145 #define SRPMINDET_100US 0x61
00146 #define SRPMINDET_1MS 0x62
00147 #define SRPMINDET_11MS 0x63
00148
00149
00153 #define Usb_build_ep_config0(type, dir, nyet) ((type<<6) | (nyet<<1) | (dir))
00154 #define Usb_build_ep_config1(size, bank ) ((size<<4) | (bank<<2) )
00155 #define usb_configure_endpoint(num, type, dir, size, bank, nyet) \
00156 ( Usb_select_endpoint(num), \
00157 usb_config_ep(Usb_build_ep_config0(type, dir, nyet),\
00158 Usb_build_ep_config1(size, bank) ))
00159
00160 #define Host_build_pipe_config0(type, token, ep_num) ((type<<6) | (token<<4) | (ep_num))
00161 #define Host_build_pipe_config1(size, bank ) ((size<<4) | (bank<<2) )
00162 #define host_configure_pipe(num, type, token,ep_num, size, bank, freq) \
00163 ( Host_select_pipe(num), \
00164 Host_set_interrupt_frequency(freq), \
00165 host_config_pipe(Host_build_pipe_config0(type, token, ep_num),\
00166 Host_build_pipe_config1(size, bank) ))
00168
00173 #define Usb_enable_regulator() (UHWCON |= (1<<UVREGE))
00175 #define Usb_disable_regulator() (UHWCON &= ~(1<<UVREGE))
00177 #define Is_usb_regulator_enabled() ((UHWCON & (1<<UVREGE)) ? TRUE : FALSE)
00179
00184 #define Usb_enable_uid_pin() (UHWCON |= (1<<UIDE))
00186 #define Usb_disable_uid_pin() (UHWCON &= ~(1<<UIDE))
00188 #define Usb_force_device_mode() (Usb_disable_uid_pin(), UHWCON |= (1<<UIMOD))
00190 #define Usb_force_host_mode() (Usb_disable_uid_pin(), UHWCON &= ~(1<<UIMOD))
00192 #define Usb_enable_uvcon_pin() (UHWCON |= (1<<UVCONE))
00194 #define Usb_disable_uvcon_pin() (UHWCON &= ~(1<<UVCONE))
00196 #define Usb_full_speed_mode() (UHWCON |= (1<<UDSS))
00198 #define Usb_low_speed_mode() (UHWCON &= ~(1<<UDSS))
00199
00201 #define Usb_enable() (USBCON |= ((1<<USBE) | (1<<OTGPADE)))
00203 #define Usb_disable() (USBCON &= ~((1<<USBE) | (1<<OTGPADE)))
00204 #define Is_usb_enabled() ((USBCON & (1<<USBE)) ? TRUE : FALSE)
00205
00207 #define Usb_enable_vbus_pad() (USBCON |= (1<<OTGPADE))
00209 #define Usb_disable_vbus_pad() (USBCON &= ~(1<<OTGPADE))
00210
00211 #define Usb_select_device() (USBCON &= ~(1<<HOST))
00212 #define Usb_select_host() (USBCON |= (1<<HOST))
00213 #define Is_usb_host_enabled() ((USBCON & (1<<HOST)) ? TRUE : FALSE)
00214 #define Is_usb_device_enabled() ((USBCON & (1<<HOST)) ? FALSE : TRUE)
00215
00217 #define Select_full_speed_operation() (UDCON &= ~(1<<LSM))
00219 #define Select_low_speed_operation() (UDCON |= (1<<LSM))
00220
00222 #define Usb_freeze_clock() (USBCON |= (1<<FRZCLK))
00223 #define Usb_unfreeze_clock() (USBCON &= ~(1<<FRZCLK))
00224 #define Is_usb_clock_freezed() ((USBCON & (1<<FRZCLK)) ? TRUE : FALSE)
00225
00226 #define Usb_enable_id_interrupt() (USBCON |= (1<<IDTE))
00227 #define Usb_disable_id_interrupt() (USBCON &= ~(1<<IDTE))
00228 #define Is_usb_id_interrupt_enabled() ((USBCON & (1<<IDTE)) ? TRUE : FALSE)
00229 #define Is_usb_id_device() ((USBSTA & (1<<ID)) ? TRUE : FALSE)
00230 #define Is_usb_id_host() ((USBSTA & (1<<ID)) ? FALSE : TRUE)
00231 #define Usb_ack_id_transition() (USBINT = ~(1<<IDTI))
00232 #define Is_usb_id_transition() ((USBINT & (1<<IDTI)) ? TRUE : FALSE)
00233
00234 #define Usb_enable_vbus_interrupt() (USBCON |= (1<<VBUSTE))
00235 #define Usb_disable_vbus_interrupt() (USBCON &= ~(1<<VBUSTE))
00236 #define Is_usb_vbus_interrupt_enabled() ((USBCON & (1<<VBUSTE)) ? TRUE : FALSE)
00237 #define Is_usb_vbus_high() ((USBSTA & (1<<VBUS)) ? TRUE : FALSE)
00238 #define Is_usb_vbus_low() ((USBSTA & (1<<VBUS)) ? FALSE : TRUE)
00239 #define Usb_ack_vbus_transition() (USBINT = ~(1<<VBUSTI))
00240 #define Is_usb_vbus_transition() ((USBINT & (1<<VBUSTI)) ? TRUE : FALSE)
00241
00243 #define Usb_get_general_interrupt() (USBINT & (USBCON & MSK_IDTE_VBUSTE))
00245 #define Usb_ack_all_general_interrupt() (USBINT = ~(USBCON & MSK_IDTE_VBUSTE))
00246 #define Usb_ack_cache_id_transition(x) ((x) &= ~(1<<IDTI))
00247 #define Usb_ack_cache_vbus_transition(x) ((x) &= ~(1<<VBUSTI))
00248 #define Is_usb_cache_id_transition(x) (((x) & (1<<IDTI)) )
00249 #define Is_usb_cache_vbus_transition(x) (((x) & (1<<VBUSTI)))
00250
00252 #define Usb_get_otg_interrupt() (OTGINT & OTGIEN)
00254 #define Usb_ack_all_otg_interrupt() (OTGINT = ~OTGIEN)
00255 #define Is_otg_cache_bconnection_error(x) (((x) & MSK_BCERRI))
00256 #define Usb_ack_cache_bconnection_error(x) ((x) &= ~MSK_BCERRI)
00257
00258 #define Usb_enter_dpram_mode() (UDPADDH = (1<<DPACC))
00259 #define Usb_exit_dpram_mode() (UDPADDH = (U8)~(1<<DPACC))
00260 #define Usb_set_dpram_address(addr) (UDPADDH = (1<<DPACC) + ((Uint16)addr >> 8), UDPADDL = (Uchar)addr)
00261 #define Usb_write_dpram_byte(val) (UEDATX=val)
00262 #define Usb_read_dpram_byte() (UEDATX)
00263
00265 #define Usb_enable_vbus() (OTGCON |= (1<<VBUSREQ))
00267 #define Usb_disable_vbus() (OTGCON |= (1<<VBUSRQC))
00269 #define Usb_enable_manual_vbus() (PORTE|=0x80,DDRE|=0x80,Usb_disable_uvcon_pin())
00271 #define Usb_disable_manual_vbus() (PORTE&=~0x80,DDRE|=0x80,Usb_enable_uvcon_pin())
00273 #define Is_usb_vbus_manual_on() (((PINE&0x80) != 0) ? TRUE : FALSE)
00274
00276 #define Usb_device_initiate_hnp() (OTGCON |= (1<<HNPREQ))
00278 #define Usb_device_stop_hnp() (OTGCON &= ~(1<<HNPREQ))
00280 #define Usb_host_accept_hnp() (OTGCON |= (1<<HNPREQ))
00282 #define Usb_host_reject_hnp() (OTGCON &= ~(1<<HNPREQ))
00284 #define Usb_device_initiate_srp() (OTGCON |= (1<<SRPREQ))
00286 #define Usb_select_vbus_srp_method() (OTGCON |= (1<<SRPSEL))
00288 #define Usb_select_data_srp_method() (OTGCON &= ~(1<<SRPSEL))
00290 #define Usb_enable_vbus_hw_control() (OTGCON &= ~(1<<VBUSHWC))
00292 #define Usb_disable_vbus_hw_control() (OTGCON |= (1<<VBUSHWC))
00294 #define Is_usb_vbus_enabled() ((OTGCON & (1<<VBUSREQ)) ? TRUE : FALSE)
00296 #define Is_usb_hnp() ((OTGCON & (1<<HNPREQ)) ? TRUE : FALSE)
00298 #define Is_usb_device_srp() ((OTGCON & (1<<SRPREQ)) ? TRUE : FALSE)
00300 #define Is_usb_device_initiating_srp() ((OTGCON & (1<<SRPREQ)) ? TRUE : FALSE)
00301
00303 #define Set_otg_custom_timer(sel) (OTGTCON = sel)
00304
00306 #define Usb_enable_suspend_time_out_interrupt() (OTGIEN |= (1<<STOE))
00308 #define Usb_disable_suspend_time_out_interrupt() (OTGIEN &= ~(1<<STOE))
00309 #define Is_suspend_time_out_interrupt_enabled() ((OTGIEN & (1<<STOE)) ? TRUE : FALSE)
00311 #define Usb_ack_suspend_time_out_interrupt() (OTGINT &= ~(1<<STOI))
00313 #define Is_usb_suspend_time_out_interrupt() ((OTGINT & (1<<STOI)) ? TRUE : FALSE)
00314
00316 #define Usb_enable_hnp_error_interrupt() (OTGIEN |= (1<<HNPERRE))
00318 #define Usb_disable_hnp_error_interrupt() (OTGIEN &= ~(1<<HNPERRE))
00319 #define Is_hnp_error_interrupt_enabled() ((OTGIEN & (1<<HNPERRE)) ? TRUE : FALSE)
00321 #define Usb_ack_hnp_error_interrupt() (OTGINT &= ~(1<<HNPERRI))
00323 #define Is_usb_hnp_error_interrupt() ((OTGINT & (1<<HNPERRI)) ? TRUE : FALSE)
00324
00326 #define Usb_enable_role_exchange_interrupt() (OTGIEN |= (1<<ROLEEXE))
00328 #define Usb_disable_role_exchange_interrupt() (OTGIEN &= ~(1<<ROLEEXE))
00329 #define Is_role_exchange_interrupt_enabled() ((OTGIEN & (1<<ROLEEXE)) ? TRUE : FALSE)
00331 #define Usb_ack_role_exchange_interrupt() (OTGINT &= ~(1<<ROLEEXI))
00333 #define Is_usb_role_exchange_interrupt() ((OTGINT & (1<<ROLEEXI)) ? TRUE : FALSE)
00334
00336 #define Usb_enable_bconnection_error_interrupt() (OTGIEN |= (1<<BCERRE))
00338 #define Usb_disable_bconnection_error_interrupt() (OTGIEN &= ~(1<<BCERRE))
00339 #define Is_bconnection_error_interrupt_enabled() ((OTGIEN & (1<<BCERRE)) ? TRUE : FALSE)
00341 #define Usb_ack_bconnection_error_interrupt() (OTGINT &= ~(1<<BCERRI))
00343 #define Is_usb_bconnection_error_interrupt() ((OTGINT & (1<<BCERRI)) ? TRUE : FALSE)
00344
00346 #define Usb_enable_vbus_error_interrupt() (OTGIEN |= (1<<VBERRE))
00348 #define Usb_disable_vbus_error_interrupt() (OTGIEN &= ~(1<<VBERRE))
00349 #define Is_vbus_error_interrupt_enabled() ((OTGIEN & (1<<VBERRE)) ? TRUE : FALSE)
00351 #define Usb_ack_vbus_error_interrupt() (OTGINT &= ~(1<<VBERRI))
00353 #define Is_usb_vbus_error_interrupt() ((OTGINT & (1<<VBERRI)) ? TRUE : FALSE)
00354
00356 #define Usb_enable_srp_interrupt() (OTGIEN |= (1<<SRPE))
00358 #define Usb_disable_srp_interrupt() (OTGIEN &= ~(1<<SRPE))
00359 #define Is_srp_interrupt_enabled() ((OTGIEN & (1<<SRPE)) ? TRUE : FALSE)
00361 #define Usb_ack_srp_interrupt() (OTGINT &= ~(1<<SRPI))
00363 #define Is_usb_srp_interrupt() ((OTGINT & (1<<SRPI)) ? TRUE : FALSE)
00365
00366
00371 #define Usb_initiate_remote_wake_up() (UDCON |= (1<<RMWKUP))
00373 #define Usb_detach() (UDCON |= (1<<DETACH))
00375 #define Usb_attach() (UDCON &= ~(1<<DETACH))
00377 #define Is_usb_pending_remote_wake_up() ((UDCON & (1<<RMWKUP)) ? TRUE : FALSE)
00379 #define Is_usb_detached() ((UDCON & (1<<DETACH)) ? TRUE : FALSE)
00380
00382 #define Usb_get_device_interrupt() (UDINT & (1<<UDIEN))
00384 #define Usb_ack_all_device_interrupt() (UDINT = ~(1<<UDIEN))
00385
00387 #define Usb_enable_remote_wake_up_interrupt() (UDIEN |= (1<<UPRSME))
00389 #define Usb_disable_remote_wake_up_interrupt() (UDIEN &= ~(1<<UPRSME))
00390 #define Is_remote_wake_up_interrupt_enabled() ((UDIEN & (1<<UPRSME)) ? TRUE : FALSE)
00392 #define Usb_ack_remote_wake_up_start() (UDINT = ~(1<<UPRSMI))
00394 #define Is_usb_remote_wake_up_start() ((UDINT & (1<<UPRSMI)) ? TRUE : FALSE)
00395
00397 #define Usb_enable_resume_interrupt() (UDIEN |= (1<<EORSME))
00399 #define Usb_disable_resume_interrupt() (UDIEN &= ~(1<<EORSME))
00400 #define Is_resume_interrupt_enabled() ((UDIEN & (1<<EORSME)) ? TRUE : FALSE)
00402 #define Usb_ack_resume() (UDINT = ~(1<<EORSMI))
00404 #define Is_usb_resume() ((UDINT & (1<<EORSMI)) ? TRUE : FALSE)
00405
00407 #define Usb_enable_wake_up_interrupt() (UDIEN |= (1<<WAKEUPE))
00409 #define Usb_disable_wake_up_interrupt() (UDIEN &= ~(1<<WAKEUPE))
00410 #define Is_swake_up_interrupt_enabled() ((UDIEN & (1<<WAKEUPE)) ? TRUE : FALSE)
00412 #define Usb_ack_wake_up() (UDINT = ~(1<<WAKEUPI))
00414 #define Is_usb_wake_up() ((UDINT & (1<<WAKEUPI)) ? TRUE : FALSE)
00415
00417 #define Usb_enable_reset_interrupt() (UDIEN |= (1<<EORSTE))
00419 #define Usb_disable_reset_interrupt() (UDIEN &= ~(1<<EORSTE))
00420 #define Is_reset_interrupt_enabled() ((UDIEN & (1<<EORSTE)) ? TRUE : FALSE)
00422 #define Usb_ack_reset() (UDINT = ~(1<<EORSTI))
00424 #define Is_usb_reset() ((UDINT & (1<<EORSTI)) ? TRUE : FALSE)
00425
00427 #define Usb_enable_sof_interrupt() (UDIEN |= (1<<SOFE))
00429 #define Usb_disable_sof_interrupt() (UDIEN &= ~(1<<SOFE))
00430 #define Is_sof_interrupt_enabled() ((UDIEN & (1<<SOFE)) ? TRUE : FALSE)
00432 #define Usb_ack_sof() (UDINT = ~(1<<SOFI))
00434 #define Is_usb_sof() ((UDINT & (1<<SOFI)) ? TRUE : FALSE)
00435
00437 #define Usb_enable_suspend_interrupt() (UDIEN |= (1<<SUSPE))
00439 #define Usb_disable_suspend_interrupt() (UDIEN &= ~(1<<SUSPE))
00440 #define Is_suspend_interrupt_enabled() ((UDIEN & (1<<SUSPE)) ? TRUE : FALSE)
00442 #define Usb_ack_suspend() (UDINT = ~(1<<SUSPI))
00444 #define Is_usb_suspend() ((UDINT & (1<<SUSPI)) ? TRUE : FALSE)
00445
00447 #define Usb_enable_address() (UDADDR |= (1<<ADDEN))
00449 #define Usb_disable_address() (UDADDR &= ~(1<<ADDEN))
00451 #define Usb_configure_address(addr) (UDADDR = (UDADDR & (1<<ADDEN)) | ((U8)addr & MSK_UADD))
00452
00454 #define Usb_frame_number() ((U16)((((U16)UDFNUMH) << 8) | ((U16)UDFNUML)))
00456 #define Is_usb_frame_number_crc_error() ((UDMFN & (1<<FNCERR)) ? TRUE : FALSE)
00458
00459
00460
00461
00466 #define Usb_select_endpoint(ep) (UENUM = (U8)ep )
00467
00469 #define Usb_get_selected_endpoint() (UENUM )
00470
00472 #define Usb_reset_endpoint(ep) (UERST = 1 << (U8)ep, UERST = 0)
00473
00475 #define Usb_enable_endpoint() (UECONX |= (1<<EPEN))
00477 #define Usb_enable_stall_handshake() (UECONX |= (1<<STALLRQ))
00479 #define Usb_reset_data_toggle() (UECONX |= (1<<RSTDT))
00481 #define Usb_disable_endpoint() (UECONX &= ~(1<<EPEN))
00483 #define Usb_disable_stall_handshake() (UECONX |= (1<<STALLRQC))
00485 #define Usb_select_epnum_for_cpu() (UECONX &= ~(1<<EPNUMS))
00487 #define Is_usb_endpoint_enabled() ((UECONX & (1<<EPEN)) ? TRUE : FALSE)
00489 #define Is_usb_endpoint_stall_requested() ((UECONX & (1<<STALLRQ)) ? TRUE : FALSE)
00490
00492 #define Usb_configure_endpoint_type(type) (UECFG0X = (UECFG0X & ~(MSK_EPTYPE)) | ((U8)type << 6))
00494 #define Usb_configure_endpoint_direction(dir) (UECFG0X = (UECFG0X & ~(1<<EPDIR)) | ((U8)dir))
00495
00497 #define Usb_configure_endpoint_size(size) (UECFG1X = (UECFG1X & ~MSK_EPSIZE) | ((U8)size << 4))
00499 #define Usb_configure_endpoint_bank(bank) (UECFG1X = (UECFG1X & ~MSK_EPBK) | ((U8)bank << 2))
00501 #define Usb_allocate_memory() (UECFG1X |= (1<<ALLOC))
00503 #define Usb_unallocate_memory() (UECFG1X &= ~(1<<ALLOC))
00504
00506 #define Usb_ack_overflow_interrupt() (UESTA0X &= ~(1<<OVERFI))
00508 #define Usb_ack_underflow_interrupt() (UESTA0X &= ~(1<<UNDERFI))
00510 #define Usb_ack_zlp() (UESTA0X &= ~(1<<ZLPSEEN))
00512 #define Usb_data_toggle() ((UESTA0X&MSK_DTSEQ) >> 2)
00514 #define Usb_nb_busy_bank() (UESTA0X & MSK_NBUSYBK)
00516 #define Is_usb_one_bank_busy() ((UESTA0X & MSK_NBUSYBK) == 0 ? FALSE : TRUE)
00518 #define Is_endpoint_configured() ((UESTA0X & (1<<CFGOK)) ? TRUE : FALSE)
00520 #define Is_usb_overflow() ((UESTA0X & (1<<OVERFI)) ? TRUE : FALSE)
00522 #define Is_usb_underflow() ((UESTA0X & (1<<UNDERFI)) ? TRUE : FALSE)
00524 #define Is_usb_zlp() ((UESTA0X & (1<<ZLPSEEN)) ? TRUE : FALSE)
00525
00527 #define Usb_control_direction() ((UESTA1X & (1<<CTRLDIR)) >> 2)
00529 #define Usb_current_bank() ( UESTA1X & MSK_CURRBK)
00530
00532 #define Usb_ack_fifocon() (UEINTX &= ~(1<<FIFOCON))
00534 #define Usb_ack_nak_in() (UEINTX &= ~(1<<NAKINI))
00536 #define Usb_ack_nak_out() (UEINTX &= ~(1<<NAKOUTI))
00538 #define Usb_ack_receive_setup() (UEINTX &= ~(1<<RXSTPI))
00540 #define Usb_ack_receive_out() (UEINTX &= ~(1<<RXOUTI), Usb_ack_fifocon())
00542 #define Usb_ack_stalled() (MSK_STALLEDI= 0)
00544 #define Usb_ack_in_ready() (UEINTX &= ~(1<<TXINI), Usb_ack_fifocon())
00546 #define Usb_kill_last_in_bank() (UENTTX |= (1<<RXOUTI))
00548 #define Is_usb_read_enabled() (UEINTX&(1<<RWAL))
00550 #define Is_usb_write_enabled() (UEINTX&(1<<RWAL))
00552 #define Is_usb_read_control_enabled() (UEINTX&(1<<TXINI))
00554 #define Is_usb_nak_out_sent() (UEINTX&(1<<NAKOUTI))
00556 #define Is_usb_receive_setup() (UEINTX&(1<<RXSTPI))
00558 #define Is_usb_receive_out() (UEINTX&(1<<RXOUTI))
00560 #define Is_usb_in_ready() (UEINTX&(1<<TXINI))
00562 #define Usb_send_in() (UEINTX &= ~(1<<FIFOCON))
00564 #define Usb_send_control_in() (UEINTX &= ~(1<<TXINI))
00566 #define Usb_free_out_bank() (UEINTX &= ~(1<<FIFOCON))
00568 #define Usb_ack_control_out() (UEINTX &= ~(1<<RXOUTI))
00569
00571 #define Usb_enable_flow_error_interrupt() (UEIENX |= (1<<FLERRE))
00573 #define Usb_enable_nak_in_interrupt() (UEIENX |= (1<<NAKINE))
00575 #define Usb_enable_nak_out_interrupt() (UEIENX |= (1<<NAKOUTE))
00577 #define Usb_enable_receive_setup_interrupt() (UEIENX |= (1<<RXSTPE))
00579 #define Usb_enable_receive_out_interrupt() (UEIENX |= (1<<RXOUTE))
00581 #define Usb_enable_stalled_interrupt() (UEIENX |= (1<<STALLEDE))
00583 #define Usb_enable_in_ready_interrupt() (UEIENX |= (1<<TXIN))
00585 #define Usb_disable_flow_error_interrupt() (UEIENX &= ~(1<<FLERRE))
00587 #define Usb_disable_nak_in_interrupt() (UEIENX &= ~(1<<NAKINE))
00589 #define Usb_disable_nak_out_interrupt() (UEIENX &= ~(1<<NAKOUTE))
00591 #define Usb_disable_receive_setup_interrupt() (UEIENX &= ~(1<<RXSTPE))
00593 #define Usb_disable_receive_out_interrupt() (UEIENX &= ~(1<<RXOUTE))
00595 #define Usb_disable_stalled_interrupt() (UEIENX &= ~(1<<STALLEDE))
00597 #define Usb_disable_in_ready_interrupt() (UEIENX &= ~(1<<TXIN))
00598
00600 #define Usb_read_byte() (UEDATX)
00602 #define Usb_write_byte(byte) (UEDATX = (U8)byte)
00603
00605 #define Usb_byte_counter() ((((U16)UEBCHX) << 8) | (UEBCLX))
00607 #define Usb_byte_counter_8() ((U8)UEBCLX)
00608
00610 #define Usb_interrupt_flags() (UEINT)
00612 #define Is_usb_endpoint_event() (Usb_interrupt_flags() != 0x00)
00614
00615
00616
00621 #define Host_allocate_memory() (UPCFG1X |= (1<<ALLOC))
00623 #define Host_unallocate_memory() (UPCFG1X &= ~(1<<ALLOC))
00624
00626 #define Host_enable() (USBCON |= (1<<HOST))
00627
00628 #ifndef SOFEN
00629 #define SOFEN 0 //For AVRGCC, SOFEN bit missing in default sfr file
00630 #endif
00632 #define Host_enable_sof() (UHCON |= (1<<SOFEN))
00634 #define Host_disable_sof() (UHCON &= ~(1<<SOFEN))
00636 #define Host_send_reset() (UHCON |= (1<<RESET))
00638 #define Host_is_reset() ((UHCON & (1<<RESET)) ? TRUE : FALSE)
00640 #define Host_send_resume() (UHCON |= (1<<RESUME))
00642 #define Host_is_resume() ((UHCON & (1<<RESUME)) ? TRUE : FALSE)
00643
00645 #define Host_enable_sof_interrupt() (UHIEN |= (1<<HSOFE))
00647 #define Host_disable_sof_interrupt() (UHIEN &= ~(1<<HSOFE))
00648 #define Is_host_sof_interrupt_enabled() ((UHIEN & (1<<HSOFE)) ? TRUE : FALSE)
00650 #define Host_is_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00651 #define Is_host_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00652 #define Host_ack_sof() (UHINT &= ~(1<<HSOFI))
00653
00655 #define Host_enable_hwup_interrupt() (UHIEN |= (1<<HWUPE))
00657 #define Host_disable_hwup_interrupt() (UHIEN &= ~(1<<HWUPE))
00658 #define Is_host_hwup_interrupt_enabled() ((UHIEN & (1<<HWUPE)) ? TRUE : FALSE)
00660 #define Host_is_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00662 #define Is_host_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00663 #define Host_ack_hwup() (UHINT &= ~(1<<HWUPI))
00664
00666 #define Host_enable_down_stream_resume_interrupt() (UHIEN |= (1<<RSMEDE))
00668 #define Host_disable_down_stream_resume_interrupt() (UHIEN &= ~(1<<RSMEDE))
00669 #define Is_host_down_stream_resume_interrupt_enabled() ((UHIEN & (1<<RSMEDE)) ? TRUE : FALSE)
00671 #define Is_host_down_stream_resume() ((UHINT & (1<<RSMEDI)) ? TRUE : FALSE)
00672 #define Host_ack_down_stream_resume() (UHINT &= ~(1<<RSMEDI))
00673
00675 #define Host_enable_remote_wakeup_interrupt() (UHIEN |= (1<<RXRSME))
00677 #define Host_disable_remote_wakeup_interrupt() (UHIEN &= ~(1<<RXRSME))
00678 #define Is_host_remote_wakeup_interrupt_enabled() ((UHIEN & (1<<RXRSME)) ? TRUE : FALSE)
00680 #define Host_is_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00682 #define Is_host_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00683 #define Host_ack_remote_wakeup() (UHINT &= ~(1<<RXRSMI))
00684
00686 #define Host_enable_device_connection_interrupt() (UHIEN |= (1<<DCONNE))
00688 #define Host_disable_device_connection_interrupt() (UHIEN &= ~(1<<DCONNE))
00689 #define Is_host_device_connection_interrupt_enabled() ((UHIEN & (1<<DCONNE)) ? TRUE : FALSE)
00691 #define Is_device_connection() (UHINT & (1<<DCONNI))
00693 #define Host_ack_device_connection() (UHINT = ~(1<<DCONNI))
00694
00696 #define Host_enable_device_disconnection_interrupt() (UHIEN |= (1<<DDISCE))
00698 #define Host_disable_device_disconnection_interrupt() (UHIEN &= ~(1<<DDISCE))
00699 #define Is_host_device_disconnection_interrupt_enabled() ((UHIEN & (1<<DDISCE)) ? TRUE : FALSE)
00701 #define Is_device_disconnection() (UHINT & (1<<DDISCI) ? TRUE : FALSE)
00703 #define Host_ack_device_disconnection() (UHINT = ~(1<<DDISCI))
00704
00706 #define Host_enable_reset_interrupt() (UHIEN |= (1<<RSTE))
00708 #define Host_disable_reset_interrupt() (UHIEN &= ~(1<<RSTE))
00709 #define Is_host_reset_interrupt_enabled() ((UHIEN & (1<<RSTE)) ? TRUE : FALSE)
00711 #define Host_ack_reset() (UHINT = ~(1<<RSTI))
00713 #define Is_host_reset() Host_is_reset()
00714
00715
00717 #define Host_vbus_request() (OTGCON |= (1<<VBUSREQ))
00719 #define Host_clear_vbus_request() (OTGCON |= (1<<VBUSRQC))
00721 #define Host_configure_address(addr) (UHADDR = addr & MSK_HADDR)
00722
00724 #define Is_host_full_speed() ((USBSTA & (1<<SPEED)) ? TRUE : FALSE)
00726
00727
00728
00733 #define Host_select_pipe(p) (UPNUM = (U8)p)
00734
00736 #define Host_get_selected_pipe() (UPNUM )
00737
00739 #define Host_enable_pipe() (UPCONX |= (1<<PEN))
00741 #define Host_disable_pipe() (UPCONX &= ~(1<<PEN))
00742
00744 #define Host_set_token_setup() (UPCFG0X = UPCFG0X & ~MSK_TOKEN_SETUP)
00746 #define Host_set_token_in() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_IN)
00748 #define Host_set_token_out() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_OUT)
00749
00751 #define Host_get_endpoint_number() (UPCFG0X & (MSK_PEPNUM))
00752
00754 #define Host_get_pipe_interrupt() (UPINT)
00755
00757 #define Host_set_interrupt_frequency(frq) (UPCFG2X = (U8)frq)
00758
00760 #define Is_pipe_configured() (UPSTAX & (1<<CFGOK))
00762 #define Is_host_one_bank_busy() ((UPSTAX & (1<<MSK_NBUSYBK)) != 0)
00764 #define Host_number_of_busy_bank() (UPSTAX & (1<<MSK_NBUSYBK))
00765
00767 #define Host_reset_pipe(p) (UPRST = 1<<p , UPRST = 0)
00768
00770 #define Host_write_byte(dat) (UPDATX = dat)
00772 #define Host_read_byte() (UPDATX)
00773
00775 #define Host_freeze_pipe() (UPCONX |= (1<<PFREEZE))
00777 #define Host_unfreeze_pipe() (UPCONX &= ~(1<<PFREEZE))
00779 #define Is_host_pipe_freeze() (UPCONX & (1<<PFREEZE))
00780
00782 #define Host_reset_pipe_data_toggle() (UPCONX |= (1<<RSTDT) )
00783
00785 #define Is_host_setup_sent() ((UPINTX & (1<<TXSTPI)) ? TRUE : FALSE)
00787 #define Is_host_control_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
00789 #define Is_host_control_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00791 #define Is_host_stall() ((UPINTX & (1<<RXSTALLI)) ? TRUE : FALSE)
00793 #define Is_host_pipe_error() ((UPINTX & (1<<PERRI)) ? TRUE : FALSE)
00795 #define Host_send_setup() (UPINTX &= ~(1<<FIFOCON))
00797 #define Host_send_control_in() (UPINTX &= ~(1<<FIFOCON))
00799 #define Host_send_control_out() (UPINTX &= ~(1<<FIFOCON))
00801 #define Host_ack_control_out() (UPINTX &= ~(1<<TXOUTI))
00803 #define Host_ack_control_in() (UPINTX &= ~(1<<RXINI))
00805 #define Host_ack_setup() (UPINTX &= ~(1<<TXSTPI))
00807 #define Host_ack_stall() (UPINTX &= ~(1<<RXSTALLI))
00808
00810 #define Host_send_out() (UPINTX &= ~(1<<FIFOCON))
00812 #define Is_host_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00814 #define Host_ack_out_sent() (UPINTX &= ~(1<<TXOUTI))
00816 #define Is_host_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
00818 #define Host_ack_in_received() (UPINTX &= ~(1<<RXINI))
00820 #define Host_send_in() (UPINTX &= ~(1<<FIFOCON))
00822 #define Is_host_nak_received() ((UPINTX & (1<<NAKEDI)) ? TRUE : FALSE)
00824 #define Host_ack_nak_received() (UPINTX &= ~(1<<NAKEDI))
00825
00826
00827
00829 #define Is_host_read_enabled() (UPINTX&(1<<RWAL))
00831 #define Is_host_write_enabled() (UPINTX&(1<<RWAL))
00832
00834 #define Host_standard_in_mode() (UPCONX &= ~(1<<INMODE))
00836 #define Host_continuous_in_mode() (UPCONX |= (1<<INMODE))
00837
00839 #define Host_in_request_number(in_num) (UPINRQX = (U8)in_num)
00841 #define Host_get_in_request_number() (UPINRQX)
00842
00844 #define Host_data_length_U8() (UPBCLX)
00846 #define Host_data_length_U16() ((((U16)UPBCHX)<<8) | UPBCLX)
00848 #define Host_byte_counter() Host_data_length_U16()
00850 #define Host_byte_counter_8() Host_data_length_U8()
00851
00853 #define Host_get_pipe_length() ((U16)0x08 << ((UPCFG1X & MSK_PSIZE)>>4))
00854
00856 #define Host_get_pipe_type() (UPCFG0X>>6)
00857
00859 #define Host_error_status() (UPERRX & MSK_ERROR)
00861 #define Host_ack_all_errors() (UPERRX = 0x00)
00862
00864 #define Host_enable_transmit_interrupt() (UPIENX |= (1<<TXOUTE))
00866 #define Host_disable_transmit_interrupt() (UPIENX &= ~(1<<TXOUTE))
00867
00869 #define Host_enable_receive_interrupt() (UPIENX |= (1<<RXINE))
00871 #define Host_disable_receive_interrupt() (UPIENX &= ~(1<<RXINE))
00872
00874 #define Host_enable_stall_interrupt() (UPIENX |= (1<<RXSTALLE))
00876 #define Host_disable_stall_interrupt() (UPIENX &= ~(1<<RXSTALLE))
00877
00879 #define Host_enable_error_interrupt() (UPIENX |= (1<<PERRE))
00881 #define Host_disable_error_interrupt() (UPIENX &= ~(1<<PERRE))
00882
00884 #define Host_enable_nak_interrupt() (UPIENX |= (1<<NAKEDE))
00886 #define Host_disable_nak_interrupt() (UPIENX &= ~(1<<NAKEDE))
00887
00888 #define Get_pipe_token(x) ((x & (0x80)) ? TOKEN_IN : TOKEN_OUT)
00889
00891
00898
00899 #define wSWAP(x) \
00900 ( (((x)>>8)&0x00FF) \
00901 | (((x)<<8)&0xFF00) \
00902 )
00903
00904
00912 #if !defined(BIG_ENDIAN) && !defined(LITTLE_ENDIAN)
00913 #error YOU MUST Define the Endian Type of target: LITTLE_ENDIAN or BIG_ENDIAN
00914 #endif
00915 #ifdef LITTLE_ENDIAN
00916 #define Usb_write_word_enum_struc(x) (x)
00917 #else //BIG_ENDIAN
00918 #define Usb_write_word_enum_struc(x) (wSWAP(x))
00919 #endif
00920
00921
00923
00924
00925
00926 U8 usb_config_ep (U8, U8);
00927 U8 usb_select_enpoint_interrupt (void);
00928 U16 usb_get_nb_byte_epw (void);
00929 U8 usb_send_packet (U8 , U8*, U8);
00930 U8 usb_read_packet (U8 , U8*, U8);
00931 void usb_halt_endpoint (U8);
00932 void usb_reset_endpoint (U8);
00933 U8 usb_init_device (void);
00934
00935 U8 host_config_pipe (U8, U8);
00936 U8 host_determine_pipe_size (U16);
00937 void host_disable_all_pipe (void);
00938 U8 usb_get_nb_pipe_interrupt (void);
00939
00940 #endif // _USB_DRV_H_
00941
