drivers/flash/flashc.c

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#include <bitops.h>
#include <interrupt.h>
#include <io.h>
#include <chip/memory-map.h>
#include <flash/flashc.h>

void flashc_adjust_wait_state(unsigned long new_hclk_rate)
{
        unsigned long   iflags;
        uint32_t        fcr;

        iflags = cpu_irq_save();

        fcr = mmio_read32((void *)FLASHC_BASE);

        /* FIXME: Max rate taken from UC3A0 data sheet */
        if (new_hclk_rate > 33000000) {
                /* Set one wait state for flash access */
                fcr |= 1 << 6;
        } else {
                /* No wait state necessary */
                fcr &= ~(1 << 6);
        }

        mmio_write32((void *)FLASHC_BASE, fcr);
        mmio_read32((void *)FLASHC_BASE);

        cpu_irq_restore(iflags);
}

void flashc_write_gp_fuse(unsigned int bit_nr)
{
        uint32_t        fcmd;

        assert(bit_nr < 64);

        fcmd = 0xa5 << 24 | bit_nr << 8 | 7;
        mmio_write32((void *)(FLASHC_BASE + 4), fcmd);
}

void flashc_erase_gp_fuse(unsigned int bit_nr)
{
        uint32_t        fcmd;

        assert(bit_nr < 64);

        fcmd = 0xa5 << 24 | bit_nr << 8 | 8;
        mmio_write32((void *)(FLASHC_BASE + 4), fcmd);
}

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