chip/at32uc3a3/include/chip/memory-map.h

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#ifndef CHIP_MEMORY_MAP_H_INCLUDED
#define CHIP_MEMORY_MAP_H_INCLUDED

/* Internal memories */
#define CPU_SRAM_BASE                   0x00000000
#define CPU_SRAM_SIZE                   0x00010000
#define FLASH_BASE                      0x80000000
#define FLASH_SIZE                      0x00040000
#define FLASH_USER_PAGE_BASE            0x80800000
#define FLASH_USER_PAGE_SIZE            0x00000200
#define HSB_SRAM_BASE                   0xff000000
#define HSB_SRAM_SIZE                   0x00010000

#define CHIP_ENTRY_VMA                  FLASH_BASE
#define CHIP_ENTRY_LMA                  FLASH_BASE

/* Used by the linker script to place the writeable data sections */
#define DATA_SRAM_BASE                  CPU_SRAM_BASE

/* Devices on the High Speed Bus (HSB) */
#define USBB_FIFO_BASE                  0xe0000000
#define DMACA_BASE                      0xff100000
#define AES_BASE                        0xfffd0000

/* Devices on Peripheral Bus A (PBA) */
#define USBB_REGS_BASE                  0xfffe0000
#define HMATRIX_BASE                    0xfffe1000
#define FLASHC_BASE                     0xfffe1400
#define SMC_BASE                        0xfffe1c00
#define SDRAMC_BASE                     0xfffe2000
#define ECCHRS_BASE                     0xfffe2400
#define BUSMON_BASE                     0xfffe2800
#define MCI_BASE                        0xfffe4000
#define MSI_BASE                        0xfffe8000

/* Devices on Peripheral Bus B (PBB) */
#define PDCA_BASE                       0xffff0000
#define INTC_BASE                       0xffff0800
#define PM_BASE                         0xffff0c00
#define RTC_BASE                        0xffff0d00
#define WDT_BASE                        0xffff0d30
#define FREQM_BASE                      0xffff0d50
#define EIC_BASE                        0xffff0d80
#define GPIO_BASE                       0xffff1000
#define USART0_BASE                     0xffff1400
#define USART1_BASE                     0xffff1800
#define USART2_BASE                     0xffff1c00
#define USART3_BASE                     0xffff2000
#define SPI0_BASE                       0xffff2400
#define SPI1_BASE                       0xffff2800
#define TWIM0_BASE                      0xffff2c00
#define TWIM1_BASE                      0xffff3000
#define SSC_BASE                        0xffff3400
#define TC0_BASE                        0xffff3800
#define ADC_BASE                        0xffff3c00
#define DAC_BASE                        0xffff4000
#define TC1_BASE                        0xffff4400
#define TWIS0_BASE                      0xffff5000
#define TWIS1_BASE                      0xffff5400

#ifndef __ASSEMBLER__
extern struct physmem_pool      cpu_sram_pool;
extern struct physmem_pool      hsb_sram_pool;
#endif

#endif /* CHIP_MEMORY_MAP_H_INCLUDED */

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