drivers/dmac/dmaca_regs.h

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#ifndef DMACA_REGS_H_INCLUDED
#define DMACA_REGS_H_INCLUDED

#define DMACA_CHAN_SAR          0x0000  
#define DMACA_CHAN_DAR          0x0008  
#define DMACA_CHAN_LLP          0x0010  
# define DMACA_LLP_LMS(x)               ((x) <<  0)     
#define DMACA_CHAN_CTLL         0x0018  
# define DMACA_CTLL_INT_EN              (  1 <<  0)     
# define DMACA_CTLL_DST_TR_WIDTH(x)     ((x) <<  1)     
# define DMACA_CTLL_SRC_TR_WIDTH(x)     ((x) <<  4)     
# define DMACA_CTLL_DINC_INCREMENT      (  0 <<  7)     
# define DMACA_CTLL_DINC_DECREMENT      (  1 <<  7)     
# define DMACA_CTLL_DINC_NO_CHANGE      (  2 <<  7)     
# define DMACA_CTLL_SINC_INCREMENT      (  0 <<  9)     
# define DMACA_CTLL_SINC_DECREMENT      (  1 <<  9)     
# define DMACA_CTLL_SINC_NO_CHANGE      (  2 <<  9)     
# define DMACA_CTLL_DST_MSIZE(x)        ((x) << 11)     
# define DMACA_CTLL_SRC_MSIZE(x)        ((x) << 14)     
# define DMACA_CTLL_TT_M2M              (  0 << 20)     
# define DMACA_CTLL_TT_M2P              (  1 << 20)     
# define DMACA_CTLL_TT_P2M              (  2 << 20)     
# define DMACA_CTLL_TT_P2P              (  3 << 20)     
# define DMACA_CTLL_DMS(x)              ((x) << 23)     
# define DMACA_CTLL_SMS(x)              ((x) << 25)     
# define DMACA_CTLL_LLP_D_EN            (  1 << 27)     
# define DMACA_CTLL_LLP_S_EN            (  1 << 28)     
#define DMACA_CHAN_CTLH         0x001c  
# define DMACA_CTLH_BLOCK_TS(x)         ((x) <<  0)     
#define DMACA_CHAN_CFGL         0x0040  
# define DMACA_CFGL_CH_PRIOR(x)         ((x) <<  5)     
# define DMACA_CH_SUSP                  (  1 <<  8)     
# define DMACA_FIFO_EMPTY               (  1 <<  9)     
#define DMACA_CHAN_CFGH         0x0044  
# define DMACA_CFGH_FCMODE              (  1 <<  0)     
# define DMACA_CFGH_FIFO_MODE           (  1 <<  1)     
# define DMACA_CFGH_SRC_PER(x)          ((x) <<  7)     
# define DMACA_CFGH_DST_PER(x)          ((x) << 11)     



#define DMACA_CHAN_REGS_SIZE    0x0058

#define DMACA_RAW_TFR           0x02c0  
#define DMACA_RAW_BLOCK         0x02c8  
#define DMACA_RAW_SRC_TRAN      0x02d0  
#define DMACA_RAW_DST_TRAN      0x02d8  
#define DMACA_RAW_ERR           0x02e0  
#define DMACA_STATUS_TFR        0x02e8  
#define DMACA_STATUS_BLOCK      0x02f0  
#define DMACA_STATUS_SRC_TRAN   0x02f8  
#define DMACA_STATUS_DST_TRAN   0x0300  
#define DMACA_STATUS_ERR        0x0308  
#define DMACA_MASK_TFR          0x0310  
#define DMACA_MASK_BLOCK        0x0318  
#define DMACA_MASK_SRC_TRAN     0x0320  
#define DMACA_MASK_DST_TRAN     0x0328  
#define DMACA_MASK_ERR          0x0330  
#define DMACA_CLEAR_TFR         0x0338  
#define DMACA_CLEAR_BLOCK       0x0340  
#define DMACA_CLEAR_SRC_TRAN    0x0348  
#define DMACA_CLEAR_DST_TRAN    0x0350  
#define DMACA_CLEAR_ERR         0x0358  
#define DMACA_STATUS_INT        0x0360  
#define DMACA_DMACFG            0x0398  
# define DMACA_DMACFG_DMA_EN            (  1 <<  0)     
#define DMACA_CH_EN             0x03a0  



struct dmaca_hw_desc {
        uint32_t        sar;    
        uint32_t        dar;    
        uint32_t        llp;    
        uint32_t        ctll;   
        uint32_t        ctlh;   
};

#define dmaca_read_reg(reg)                                     \
        mmio_read32((void *)(DMACA_BASE + DMACA_##reg))

#define dmaca_write_reg(reg, value)                             \
        mmio_write32((void *)(DMACA_BASE + DMACA_##reg), value)

#define dmaca_chan_read_reg(chan, reg)                          \
        mmio_read32(chan->regs + DMACA_CHAN_##reg)

#define dmaca_chan_write_reg(chan, reg, value)                  \
        mmio_write32(chan->regs + DMACA_CHAN_##reg, value)

#define dmaca_set_chan_bit(chan, reg)                           \
        dmaca_write_reg(reg, (chan->mask << 8) | chan->mask)

#define dmaca_clear_chan_bit(chan, reg)                         \
        dmaca_write_reg(reg, chan->mask << 8)

#define dmaca_test_chan_bit(chan, reg)                          \
        (dmaca_read_reg(reg) & chan->mask)

#endif /* DMACA_REGS_H_INCLUDED */

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